EP2S90F1020C3N Altera, EP2S90F1020C3N Datasheet - Page 14

• Manufacturer Part Number: EP2S90F1020C3N
• Description: IC STRATIX II FPGA 90K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S90F1020C3N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520488
• Number Of I /o: 758
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 758
• Frequency (max): 816.99MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520488
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Adaptive Logic Modules
Figure 2–4. LAB-Wide Control Signals
Adaptive Logic
Modules
2–6
Stratix II Device Handbook, Volume 1
Dedicated Row LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
6
6
signal with asynchronous load data input tied high. When the
asynchronous load/preset signal is used, the labclkena0 signal is no
longer available.
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrack
skew allows clock and control signal distribution in addition to data.
Figure 2–4
The basic building block of logic in the Stratix II architecture, the adaptive
logic module (ALM), provides advanced features with efficient logic
utilization. Each ALM contains a variety of look-up table (LUT)-based
resources that can be divided between two adaptive LUTs (ALUTs). With
up to eight inputs to the two ALUTs, one ALM can implement various
combinations of two functions. This adaptability allows the ALM to be
6
labclk0
clock signals per LAB.
There are two unique
shows the LAB control signal generation circuit.
or asyncload
or labpreset
labclkena0
labclk1
labclkena1
labclk2
labclkena2
TM
interconnect's inherent low
syncload
labclr0
Altera Corporation
labclr1
May 2007
synclr