EP2S90F1020C3N Altera, EP2S90F1020C3N Datasheet - Page 37

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EP2S90F1020C3N

Manufacturer Part Number
EP2S90F1020C3N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C3N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
816.99MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S90F1020C3N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S90F1020C3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S90F1020C3N
Manufacturer:
ALTERA
0
Altera Corporation
May 2007
Notes to
(1)
Simple dual-port memory
mixed width support
True dual-port memory
mixed width support
Power-up conditions
Register clears
Mixed-port read-during-write Unknown output/old data Unknown output/old data Unknown output
Configurations
Table 2–3. TriMatrix Memory Features (Part 2 of 2)
The M-RAM block does not support memory initializations. However, the M-RAM block can emulate a ROM
function using a dual-port RAM bock. The Stratix II device must write to the dual-port memory once and then
disable the write-enable ports afterwards.
Memory Feature
Table
2–3:
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient
application support. The Quartus II software automatically partitions the
user-defined memory into the embedded memory blocks using the most
efficient size combinations. You can also manually assign the memory to
a specific block size or a mixture of block sizes.
When applied to input registers, the asynchronous clear signal for the
TriMatrix embedded memory immediately clears the input registers.
However, the output of the memory block does not show the effects until
the next clock edge. When applied to output registers, the asynchronous
clear signal clears the output registers and the effects are seen
immediately.
Output registers
Outputs cleared
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
M512 RAM Block
(32 × 18 Bits)
v
Outputs cleared
Output registers
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
M4K RAM Block
(128 × 36 Bits)
v
v
Stratix II Device Handbook, Volume 1
Outputs unknown
Output registers
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
Stratix II Architecture
(4K × 144 Bits)
M-RAM Block
v
v
2–29

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