EP2S90F1020C3N Altera, EP2S90F1020C3N Datasheet - Page 58

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EP2S90F1020C3N

Manufacturer Part Number
EP2S90F1020C3N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020C3N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
816.99MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Part Number:
EP2S90F1020C3N
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ALTERA
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Part Number:
EP2S90F1020C3N
Manufacturer:
Altera
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Part Number:
EP2S90F1020C3N
Manufacturer:
ALTERA
0
PLLs & Clock Networks
Figure 2–32. Regional Clocks
2–50
Stratix II Device Handbook, Volume 1
RCLK[3..0]
RCLK[7..4]
CLK[3..0]
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-regional
clock by driving two regional clock network lines in adjacent quadrants
(one from each quadrant). This allows logic that spans multiple
quadrants to utilize the same low skew clock. The routing of this clock
signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single
quadrant. Internal logic-array routing can also drive a dual-regional
clock. Clock pins and enhanced PLL outputs on the top and bottom can
drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on
the left and right can drive vertical dual-regional clocks, as shown in
Figure
2–33. Corner PLLs cannot drive dual-regional clocks.
RCLK[31..28]
RCLK[11..8]
CLK[7..4]
RCLK[15..12]
RCLK[27..24]
CLK[15..12]
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins,
PLLs or Core Logic within that Quadrant
CLK[11..8]
RCLK[19..16]
RCLK[23..20]
Altera Corporation
May 2007

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