EP2S90F1020C3N Altera, EP2S90F1020C3N Datasheet - Page 67

• Manufacturer Part Number: EP2S90F1020C3N
• Description: IC STRATIX II FPGA 90K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S90F1020C3N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520488
• Number Of I /o: 758
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 758
• Frequency (max): 816.99MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520488
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
May 2007
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Clock multiplication and division
Phase shift
Clock switchover
PLL reconfiguration
Reconfigurable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Number of feedback clock inputs
Table 2–10. Stratix II PLL Features
For enhanced PLLs, m ranges from 1 to 256, while n and post-scale counters range from 1 to 512 with 50% duty
cycle.
For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
For degree increments, Stratix II devices can shift all output frequencies in increments of at least 45. Smaller degree
increments are possible depending on the frequency and divide parameters.
Stratix II fast PLLs only support manual clock switchover.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
Every Stratix II device has at least two enhanced PLLs with one single-ended or differential external feedback input
per PLL.
Table
Feature
2–10:
Table 2–10
devices.
Down to 125-ps increments (3),
Three differential/six single-ended
One single-ended or differential
m/(n × post-scale counter)
shows the enhanced PLL and fast PLL features in Stratix II
Enhanced PLL
(7),
v
v
v
v
v
6
(8)
(1)
(4)
Stratix II Device Handbook, Volume 1
Down to 125-ps increments (3),
m/(n × post-scale counter)
Fast PLL
Stratix II Architecture
v
v
v
v
(6)
4
(5)
(2)
2–59
(4)