EP2S90F1508I4 Altera, EP2S90F1508I4 Datasheet - Page 115

IC STRATIX II FPGA 90K 1508-FBGA

EP2S90F1508I4

Manufacturer Part Number
EP2S90F1508I4
Description
IC STRATIX II FPGA 90K 1508-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1508I4

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
902
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1923
EP2S90F1508I4

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IEEE Std. 1149.1
JTAG Boundary-
Scan Support
Altera Corporation
May 2007
SII51003-4.2
All Stratix
boundary-scan test (BST) circuitry that complies with the IEEE
Std. 1149.1. JTAG boundary-scan testing can be performed either before
or after, but not during configuration. Stratix II devices can also use the
JTAG port for configuration with the Quartus
using either Jam Files (.jam) or Jam Byte-Code Files (.jbc).
Stratix II devices support IOE I/O standard setting reconfiguration
through the JTAG BST chain. The JTAG chain can update the I/O
standard for all input and output pins any time before or during user
mode through the CONFIG_IO instruction. You can use this capability
for JTAG testing before configuration when some of the Stratix II pins
drive or receive from other devices on the board using voltage-referenced
standards. Because the Stratix II device may not be configured before
JTAG testing, the I/O pins may not be configured for appropriate
electrical standards for chip-to-chip communication. Programming those
I/O standards via JTAG allows you to fully test I/O connections to other
devices.
A device operating in JTAG mode uses four required pins, TDI,TDO, TMS,
and TCK, and one optional pin, TRST. The TCK pin has an internal weak
pull-down resistor, while the TDI,TMS and
pull-ups. The JTAG input pins are powered by the 3.3-V VCCPD pins. The
TDO output pin is powered by the V
Stratix II devices also use the JTAG port to monitor the logic operation of
the device with the SignalTap
devices support the JTAG instructions shown in
1
The Stratix II device instruction register length is 10 bits and the
USERCODE register length is 32 bits.
boundary-scan register length and device IDCODE information for
Stratix II devices.
Stratix II, Stratix, Cyclone
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II, Stratix,
Cyclone II, or Cyclone devices are in the 18th of further position,
they fail configuration. This does not affect SignalTap II.
®
II devices provide Joint Test Action Group (JTAG)
3. Configuration & Testing
®
II embedded logic analyzer. Stratix II
®
Tables 3–2
II, and Cyclone devices must be
CCIO
power supply of bank 4.
TRST
®
and
II software or hardware
pins have weak internal
Table
3–3
3–1.
show the
3–1

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