EP2S90F1508I4 Altera, EP2S90F1508I4 Datasheet - Page 214

• Manufacturer Part Number: EP2S90F1508I4
• Description: IC STRATIX II FPGA 90K 1508-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S90F1508I4

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520488
• Number Of I /o: 902
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1508-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1923; EP2S90F1508I4

Duty Cycle Distortion
Figure 5–8. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
5–78
Stratix II Device Handbook, Volume 1
clk
INPUT
VCC
Figure 5–7. Duty Cycle Distortion
DCD expressed in absolution derivation, for example, D1 or D2 in
Figure
percentage, and the percentage number is clock-period dependent. DCD
as a percentage is defined as
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions
present on the input clock signal or caused by the clock input buffer or
different input I/O standard does not transfer to the output signal.
IOE
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
5–7, is clock-period independent. DCD can also be expressed as a
NOT
inst1
CLKH = T/2
Falling Edge A
DFF
inst
Ideal Falling Edge
Clock Period (T)
D
CLRN
PRN
D1
Q
D2
(Figure
Falling Edge B
CLKL = T/2
5–8). Therefore, any DCD
OUTPUT
Altera Corporation
output
April 2011