EP2S90F1508I4 Altera, EP2S90F1508I4 Datasheet - Page 42

IC STRATIX II FPGA 90K 1508-FBGA

EP2S90F1508I4

Manufacturer Part Number
EP2S90F1508I4
Description
IC STRATIX II FPGA 90K 1508-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1508I4

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
902
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1923
EP2S90F1508I4

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TriMatrix Memory
Figure 2–22. M4K RAM Block LAB Row Interface
2–34
Stratix II Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnect
M4K RAM Block Local
Interconnect Region
16
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
You cannot use an initialization file to initialize the contents of an M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
datain
control
signals
clocks
LAB Row Clocks
M4K RAM
address
Block
dataout
byte
enable
36
6
Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnect
May 2007

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