XC3020A-7PC84C Xilinx Inc, XC3020A-7PC84C Datasheet
XC3020A-7PC84C
Specifications of XC3020A-7PC84C
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XC3020A-7PC84C Summary of contents
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... VQFP) options • Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-tested devices - Excellent reliability record Max Logic Device Gates XC3020A, 3020L, 3120A 1,500 XC3030A, 3030L, 3130A 2,000 XC3042A, 3042L, 3142A, 3142L 3,000 XC3064A, 3064L, 3164A 4,500 XC3090A, 3090L, 3190A, 3190L ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Introduction XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program ...
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Product Obsolete or Under Obsolescence R Improvements in the XC3000A and XC3000L Families The XC3000A and XC3000L families offer the following enhancements over the popular XC3000 family: The XC3000A and XC3000L families have additional inter- connect resources to drive the ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Detailed Functional Description The perimeter of configurable Input/Output Blocks (IOBs) provides a programmable interface between the internal logic array and the device package pins. The array of Con- figurable ...
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Product Obsolete or Under Obsolescence R Read or Write Data Figure 3: Static Configuration Memory Cell loaded with one bit of configuration program and con- trols one program selection in the Field Programmable Gate Array. The memory cell ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays The input-buffer portion of each IOB provides threshold detection to translate external signals applied to the pack- age pin to internal logic levels. The global input-buffer threshold of the ...
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... The array of CLBs provides the functional elements from which the user’s logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. For example, the XC3020A has 64 such blocks arranged in 8 rows and 8 columns. The development system is used to compile the configuration data which loaded into the internal configuration memory to define the operation and interconnection of each block ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Flexible routing allows use of common or individual CLB clocking. The combinatorial-logic portion of the CLB uses look-up table to implement Boolean functions. Variables selected ...
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Product Obsolete or Under Obsolescence R Count Enable Parallel Enable Clock Dual Function of 4 Variables D0 D1 Function of 5 Variables D2 Function of 6 Variables Figure 7: Counter. The modulo-8 binary counter with parallel enable and clock enable ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Figure 9: Design Editor Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect ...
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Product Obsolete or Under Obsolescence R Figure 10: FPGA General-Purpose Interconnect. Composed of a grid of metal segments that may be inter- connected through switch matrices to form networks for CLB and IOB inputs and outputs. Figure 11: Switch Matrix ...
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... Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Global Buffer Direct Input * Unbonded IOBs (6 Places) Figure 13: XC3020A Die-Edge IOBs. The XC3020A die-edge IOBs are provided with direct access to adjacent CLBs. 7-14 Global Buffer Inerconnect Alternate Buffer Direct Input November 9, 1998 (Version 3.1) ...
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... Longlines. Two additional Longlines are located adjacent to the outer sets of switching matrices. In devices larger than the XC3020A and XC3120A FPGAs, two vertical Longlines in each col- Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in each row and column ...
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... Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-state buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two non-clock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as connectable half-length lines. ...
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... HG P40 P41 Figure 18: Design Editor. An extra large view of possible interconnections in the lower right corner of the XC3020A. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays of the 3-state buffer controls allows them to implement wide multiplexing functions. Any 3-state buffer input can be selected as drive for the horizontal long-line bus by apply- ing a Low logic level on its 3-state control line ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Crystal Oscillator Figure 18 also shows the location of an internal high speed inverting amplifier that may be used to implement an on-chip crystal oscillator associated with ...
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... Mode Pins Program Mode Low on DONE/PROGRAM and RESET Clear Is ~ 200 Cycles for the XC3020A—130 to 400 s ~ 250 Cycles for the XC3030A—165 to 500 s ~ 290 Cycles for the XC3042A—195 to 580 s ~ 330 Cycles for the XC3064A—220 to 660 s ~ 375 Cycles for the XC3090A—250 to 750 s shows the state sequences ...
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... Frame # 196 > 111 0 <Data Frame # 197 > 111 1111 *The LCA Device Require Four Dummy Bits Min; Software Generates Eight Dummy Bits XC3020A XC3020L Device XC3120A Gates 1,000 to 1,500 CLBs Row x Col ( IOBs Flip-flops Horizontal Longlines TBUFs/Horizontal LL ...
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... The different FPGAs have different sizes and numbers of data frames. To maintain compatibility between various device types, the Xilinx product families use com- patible configuration formats. For the XC3020A, configura- tion requires 14779 bits for each device, arranged in 197 data frames. An additional 40 bits are used in the header. ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays be used to drive the remaining unused routing, as that might affect timing of user nets. Tie can be omitted for quick breadboard iterations where a few additional milliamps ...
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Product Obsolete or Under Obsolescence R Special Configuration Functions The configuration data includes control over several spe- cial functions in addition to the normal user logic functions and interconnect. • Input thresholds • Readback disable • DONE pull-up resistor • ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays RESET Timing As with DONE timing, the timing of the release of the inter- nal reset can be controlled to occur either a CCLK cycle before, or after, the ...
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Product Obsolete or Under Obsolescence R Configuration Timing This section describes the configuration modes in detail. Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the DIN input. ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays CCLK (Output DSCK Serial Data In n Serial DOUT n – 3 (Output) Description Data In setup CCLK Data In hold Notes power-up, V must ...
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Product Obsolete or Under Obsolescence R Master Parallel Mode In Master Parallel mode, the lead FPGA directly addresses an industry-standard byte-wide EPROM and accepts eight data bits right before incrementing (or decrementing) the address outputs. The eight data bits are ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays A0-A15 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description To address valid To data setup RCLK To data hold RCLK High RCLK Low Notes power-up, V ...
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Product Obsolete or Under Obsolescence R Peripheral Mode Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS inputs to accept byte-wide data from a microprocessor bus. In the lead FPGA, this ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays WRITE TO FPGA WS, CS0, CS1 CS2 T CA D0-D7 CCLK 4 RDY/BUSY DOUT Description Effective Write time required (Assertion of CS0, CS1, CS2, WS) DIN Setup time required ...
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Product Obsolete or Under Obsolescence R Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input(s) of the FPGA(s). The serial configuration bitstream must be available at the DIN input of the lead FPGA a short ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays DIN Bit DCC CCLK DOUT (Output) Description To DOUT DIN setup CCLK DIN hold High time Low time (Note 1) Frequency Notes: 1. The max limit ...
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Product Obsolete or Under Obsolescence R Program Readback Switching Characteristics DONE/PROG (OUTPUT) RTRIG (M0) 4 CCLK( CCRD HI-Z M1 Input/ RDATA Output Description RTRIG RTRIG High RTRIG setup RDATA delay CCLK High time Low time Notes: 1. During ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays General XC3000 Series Switching Characteristics RESET M0/M1/ DONE/PROG INIT User State (Output) PWRDWN V (Valid) CC Description M0, M1, M2 setup time required RESET ...
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Product Obsolete or Under Obsolescence R Device Performance The XC3000 families of FPGAs can achieve very high per- formance. This is the result of • A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays 1.00 0.80 0.60 0.40 0.20 – 55 – 40 – 20 Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations 300 250 200 150 ...
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... CLB outputs toggling at the clock frequency. Typical global clock-buffer power is between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz for the XC3090A. The internal capacitive load is more a function of interconnect than fan-out. With a typical load of three general interconnect segments, each CLB output requires about 0 ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Pin Descriptions Permanently Dedicated Pins V CC Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight ...
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Product Obsolete or Under Obsolescence R AND of several slave mode devices, a hold-off signal for a master mode device. After configuration this pin becomes a user-programmable I/O pin. BCLKIN This is a direct CMOS level input to the alternate ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Pin Functions During Configuration Configuration Mode <M2:M1:M0> SLAVE MASTER- MASTER- SERIAL SERIAL PERIPH HIGH <1:1:1> <0:0:0> <1:0:1> <1:1:0> POWR POWER POWER POWER DWN DWN DWN DWN (I) (I) (I) ...
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... Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed 100 mA per V pin. The number of ground pins varies from the XC3020A to the XC3090A Not tested. Allow an undriven pin to float High. For any other purposes use an external pull-up. ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage ...
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Product Obsolete or Under Obsolescence R XC3000A CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input ...
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Product Obsolete or Under Obsolescence R XC3000A IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000A IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output ...
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Product Obsolete or Under Obsolescence R XC3000L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000L Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage ...
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Product Obsolete or Under Obsolescence R XC3000L CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input ...
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Product Obsolete or Under Obsolescence R XC3000L IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000L IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output ...
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Product Obsolete or Under Obsolescence R XC3100A Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage ...
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Product Obsolete or Under Obsolescence R XC3100A CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input ...
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Product Obsolete or Under Obsolescence R XC3100A IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100A IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output ...
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Product Obsolete or Under Obsolescence R XC3100L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100L Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage ...
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Product Obsolete or Under Obsolescence R XC3100L CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input ...
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Product Obsolete or Under Obsolescence R XC3100L IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100L IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output ...
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Product Obsolete or Under Obsolescence R XC3000 Series Pin Assignments Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 208. Each chip is ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000 Series 64-Pin Plastic VQFP Pinouts XC3000A, XC3000L, and XC3100A families have identical pinouts Pin No. XC3030A 1 A0-WS-I/O 2 A1-CS2-I/O 3 A2-I/O 4 A3-I/O 5 A4-I/O 6 A14-I/O ...
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... XC3020A, which has 74 pads; therefore the corresponding pins on the 84-pin packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a dash (—) in the 68 PLCC column, have no connection to the 68 PLCC, but are connected to the 84-pin packages. ...
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... Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin definition than XC3020A/XC3030A/XC3042A. 7-68 PLCC Pin Number ...
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... XC3042A that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the XC3030A, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist on the XC3020A, which has 74 pads; therefore, the corresponding pins have no connections. (See table on page November 9, 1998 (Version 3 ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA PGA Pin XC3042A Pin Number XC3064A Number C4 GND B13 A1 ...
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Product Obsolete or Under Obsolescence R XC3000 Series 144-Pin Plastic TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts XC3042A Pin XC3064A Number XC3090A 1 PWRDN 2 I/O-TCLKIN 3 I/O* 4 I/O 5 I/O 6 I/O* 7 I/O ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000 Series 160-Pin PQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PQFP Pin XC3064A, XC3090A, PQFP Pin Number XC3195A Number 1 I/ I/O* 42 ...
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Product Obsolete or Under Obsolescence R XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA Pin PGA Pin XC3090A, XC3195A Number Number B2 PWRDN D13 D4 TCLKIN-I/O B14 B3 I/O C14 ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000 Series 176-Pin TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin Pin XC3090A Number Number 1 PWRDWN 45 2 TCLKIN-I I ...
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Product Obsolete or Under Obsolescence R XC3000 Series 208-Pin PQFP Pinouts XC3000A, and XC3000L families have identical pinouts Pin Number XC3090A Pin Number 1 – GND 54 3 PWRDWN 55 4 TCLKIN-I I I/O ...
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Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3195A PQ208 Pinouts Pin Description PQ208 Pin Description A9-I/O 206 A10-I/O 205 I/O 204 I/O 203 I/O 202 I/O 201 RDY/BUSY-RCLK-I/O A8-I/O 200 A11-I/O 199 I/O 198 I/O 197 ...
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... Product Obsolete or Under Obsolescence R Product Availability Pins Plast. Plast. Plast. Type PLCC VQFP PLCC Code PC44 VQ64 PC68 -7 CI XC3020A - XC3030A - XC3042A -6 -7 XC3064A -6 -7 XC3090A -6 XC3020L -8 XC3030L -8 CI XC3042L -8 XC3064L -8 XC3090L - XC3120A - - XC3130A - - XC3142A - XC3164A - XC3190A - XC3195A ...
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... Plast. Plast. Type PLCC VQFP PLCC Code PC44 VQ64 PC68 XC3142L XC3190L Notes Commercial + Number of Available I/O Pins Max I/O 44 XC3020A/XC3120A 64 XC3030A/XC3130A 80 34 XC3042A/3142A 96 XC2064A/XC3164A 120 XC3090A/XC3190A 144 XC3195A 176 Ordering Information Example: Device Type Speed Grade Revision History Date 11/98 Revised version number to 3 ...