XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 18

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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Table 14: DC Characteristics of User I/Os Using
Single-Ended Standards
DS557 (v4.1) April 1, 2011
Product Specification
PCI33_3
PCI66_3
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
IOSTANDARD
Attribute
(4)
(4)
(3)
(3)
(3)
(3)
(3)
(3)
24
16
24
12
16
12
8
4
6
12
16
24
12
16
12
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
2
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(mA)
Conditions
I
1.5
1.5
12
16
24
12
16
24
12
16
24
12
16
12
OL
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
Test
(mA)
–0.5
–0.5
–12
–16
–24
–12
–16
–24
–12
–16
–24
–12
–16
–12
I
–2
–4
–6
–8
–2
–4
–6
–8
–2
–4
–6
–8
–2
–4
–6
–8
–2
–4
–6
–8
–2
–4
–6
OH
10% V
10% V
Max (V)
V
0.4
0.4
0.4
0.4
0.4
0.4
Characteristics
OL
Logic Level
CCO
CCO
V
V
V
V
V
90% V
90% V
CCO
CCO
CCO
CCO
CCO
Min (V)
V
2.4
OH
CCO
CCO
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0.4
0.4
0.4
0.4
0.4
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 14: DC Characteristics of User I/Os Using
Single-Ended Standards (Cont’d)
Notes:
1.
2.
3.
4.
5.
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
IOSTANDARD
The numbers in this table are based on the conditions set forth in
Table 10
Descriptions of the symbols used in this table are as follows:
I
I
V
V
V
V
For the LVCMOS and LVTTL standards: the same V
limits apply for the Fast, Slow and QUIETIO slew attributes.
Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see
design_resources/conn_central/protocols/pci_pcix.htm. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
“Using I/O Resources” in UG331.
OL
OH
OL
OH
CCO
TT
Attribute
(5)
(5)
(5)
the output current condition under which V
the output current condition under which V
the output voltage that indicates a Low logic level
the voltage applied to a resistor termination
the output voltage that indicates a High logic level
(5)
the supply voltage for output drivers
(5)
and
Table
13.
(mA)
Conditions
13.4 –13.4 V
16.2 –16.2
I
6.7
8.1
24
16
24
16
OL
8
8
8
Test
(mA)
–6.7
–8.1
–16
–16
I
–8
–8
–8
–8
–8
OH
V
V
V
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V
V
TT
TT
Max (V)
TT
TT
TT
TT
V
– 0.475
– 0.603
0.4
0.4
0.4
0.4
0.4
Characteristics
– 0.61
– 0.81
OL
– 0.6
– 0.8
Logic Level
OL
OH
is tested
is tested
V
V
V
V
V
V
V
V
V
OL
V
V
TT
TT
Min (V)
CCO
CCO
CCO
CCO
CCO
TT
TT
TT
TT
V
and V
+ 0.475
+ 0.603
+ 0.61
+ 0.81
OH
+ 0.6
+ 0.8
- 0.4
- 0.4
- 0.4
- 0.4
- 0.4
OH
18

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