XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 3

• Manufacturer Part Number: XC3S200AN-4FTG256C
• Description: IC SPARTAN-3AN FPGA 200K 256FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

• Total Ram Bits: 294912
• Number Of Logic Elements/cells: 4032
• Number Of Labs/clbs: 448
• Number Of I /o: 195
• Number Of Gates: 200000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 4032
• No. Of Gates: 200000
• No. Of Macrocells: 4032
• Family Type: Spartan-3AN
• No. Of Speed Grades: 4
• No. Of I/o's: 195
• Package: 256FTBGA
• Family Name: Spartan®-3AN
• Device Logic Units: 4032
• Device System Gates: 200000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 195
• Ram Bits: 294912
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1553

Architectural Overview
The Spartan-3AN FPGA architecture is compatible with that
of the Spartan-3A FPGA. The architecture consists of five
fundamental programmable functional elements:
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X-Ref Target - Figure 1
DS557 (v4.1) April 1, 2011
Product Specification
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. They support a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Notes:
1.
The XC3S700AN and XC3S1400AN have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50AN has only two DCMs at the top and only one Block RAM/Multiplier column.
DCM
CLBs
IOBs
IOBs
OBs
DCM
DCM
Figure 1: Spartan-3AN Family Architecture
Spartan-3AN FPGA Family: Introduction and Ordering Information
DCM
www.xilinx.com
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These elements are organized as shown in
ring of staggered IOBs surrounds a regular array of CLBs.
Each device has two columns of block RAM except for the
XC3S50AN, which has one column. Each RAM column
consists of several 18-Kbit RAM blocks. Each block RAM is
associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device. The XC3S50AN has DCMs only at the
top, while the XC3S700AN and XC3S1400AN add two
DCMs in the middle of the two columns of block RAM and
multipliers.
The Spartan-3AN FPGA features a rich network of traces
that interconnect all five functional elements, transmitting
signals among them. Each functional element has an
associated switch matrix that permits multiple connections
to the routing.
IOBs
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
CLB
DS557-1_01_122006
Figure
1. A dual
3