XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 36

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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Output Propagation Times
Table 27: Timing for the IOB Output Path
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
Clock-to-Output Times
Propagation Times
Set/Reset Times
T
Symbol
The numbers in this table are tested using the methodology presented in
Table 10
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from
T
T
T
IOGSRQ
IOCKP
IOSRP
IOOP
and
Table
When reading from the Output
Flip-Flop (OFF), the time from the
active transition at the OCLK input to
data appearing at the Output pin
The time it takes for data to travel from
the IOB’s O input to the Output pin
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
13.
Description
LVCMOS25
drive, Fast slew rate
LVCMOS25
drive, Fast slew rate
LVCMOS25
drive, Fast slew rate
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Conditions
(2)
(2)
(2)
Table
, 12 mA output
, 12 mA output
, 12 mA output
Table 30
29.
and are based on the operating conditions set forth in
Device
All
All
All
Max
2.87
2.78
3.63
8.62
Speed Grade
-5
Max
3.13
2.91
3.89
9.65
-4
Units
ns
ns
ns
ns
36

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