XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 54

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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Table 40: Switching Characteristics for the DLL (Cont’d)
Digital Frequency Synthesizer (DFS)
Table 41: Recommended Operating Conditions for the DFS
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
5.
Notes:
1.
2.
3.
4.
Delay Lines
DCM_DELAY_STEP
Input Frequency Ranges
F
Input Clock Jitter Tolerance
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
CLKIN
The numbers in this table are based on the operating conditions set forth in
Indicates the maximum amount of output jitter that th
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter
of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps.
The typical delay step size is 23 ps.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
Symbol
CLKIN_FREQ_FX
Symbol
(5)
(2)
Finest delay resolution, average over all taps
(4)
Frequency for the CLKIN input
Cycle-to-cycle jitter at the
CLKIN input, based on CLKFX
output frequency
Period jitter at the CLKIN input
Description
e DCM adds to the jitter on the CLKIN input.
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
F
F
CLKFX
CLKFX
< 150 MHz
> 150 MHz
Table 10
and
Device
All
Table
0.200
Min
39.
Min
15
-5
333
±300
±150
Speed Grade
Max
±1
-5
(3)
Speed Grade
Max
35
0.200
Min
Min
15
-4
-4
333
Table
±300
±150
Max
±1
Max
(3)
35
39.
Units
MHz
Units
ps
ps
ns
ps
54

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