XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 64

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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Slave Parallel Mode Timing
X-Ref Target - Figure 15
Table 56: Timing for the Slave Parallel Configuration Mode
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
(Open-Drain)
Notes:
1.
2.
Setup Times
T
T
T
Hold Times
T
T
T
Clock Timing
T
T
F
SMDCC
SMCSCC
SMCCW
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
RDWR_B
PROG_B
Symbol
The numbers in this table are based on the operating conditions set forth in
Some Xilinx documents refer to Parallel modes as SelectMAP modes.
It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0–D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0–D7 bus.
To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332, Chapter 7, section “Non-Continuous SelectMAP Data
Loading” for more details.
D0 - D7
(Inputs)
INIT_B
(Input)
CSI_B
(Input)
(Input)
(Input)
CCLK
(2)
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
Setup time on the CSI_B pin before the rising transition at the CCLK pin
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal
at the CCLK input pin
Figure 15: Waveforms for Slave Parallel Configuration
T
SMCCW
T
SMDCC
No bitstream compression
With bitstream compression
Description
Byte 0
T
SMCSCC
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
T
SMCCD
Byte 1
Table
10.
T
T
MCCH
SCCH
1/F
CCPAR
All Speed Grades
Byte n
Min
1.0
15
7
7
0
0
5
5
0
0
T
T
SCCL
T
MCCL
SMCCCS
Byte n+1
Max
80
80
DS529-3_02_051607
T
SMWCC
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
64

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