XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 66

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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Table 58: Configuration Timing Requirements for Attached SPI Serial Flash
Byte Peripheral Interface (BPI) Configuration Timing
X-Ref Target - Figure 17
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
T
T
T
T
f
C
(Open-Drain)
CCS
DSU
DH
V
Symbol
PROG_B
LDC[2:0]
or f
PUDC_B
CSO_B
A[25:0]
These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
Subtract additional printed circuit board routing delay as required by the application.
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
CCLK
D[7:0]
R
HDC
Shaded values indicate specifications on attached parallel NOR Flash PROM.
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
Maximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
Figure 17: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
T
MINIT
<0:1:0>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Description
000_0000
T
CCLK1
Byte 0
www.xilinx.com
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Spartan-3AN FPGA Family: DC and Switching Characteristics
T
INITADDR
000_0001
Byte 1
T
AVQV
T
T
Data
T
CCS
DSU
V
f
T
C
New ConfigRate active
DH
T
T
Requirement
CCLK1
Address
MCCLn
T
-------------------------------- -
T
T
T
CCO
CCLKn min
MCCL1
MCCL1
Data
T
T
MCCH1
DCC
1
T
T
Address
CCLKn
DCC
T
T
CCO
CCO
Data
DS557-3_16_032009
Address
T
Data
CCD
Units
MHz
ns
ns
ns
ns
66

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