XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 69

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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Revision History
The following table shows the revision history for this document.
DS557 (v4.1) April 1, 2011
Product Specification
02/26/07
08/16/07
08/31/07
09/12/07
09/24/07
12/12/07
06/02/08
11/19/09
12/02/10
04/01/11
Date
Version
2.0.1
2.0.2
1.0
2.0
2.1
3.0
3.1
3.2
4.0
4.1
Initial release.
Updated for Production release of initial device (XC3S200AN). Timing specifications updated for v1.38
speed files. DC specifications updated with production values. Other changes throughout.
Updated for Production release of XC3S1400AN. Improved t
Updated for Production release of XC3S700AN.
Updated for Production release of XC3S400AN. Updated
Production speed files are available as of Service Pack 3. Removed PCIX IOSTANDARD due to limited
PCIX interface support. Added note that SPI_ACCESS (In-System Flash) is not currently supported in
simulation.
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
SPI_ACCESS simulation is supported in ISE 10.1 software. Removed DNA_RETENTION limit of 10
years in
Propagation Times for the IOB Input Path to show values by device in
SSO recommendation for SSTL18_II in
synchronous to CCLK rising edge. Updated links.
Improved V
Clarified power sequencing in Note
Operating Conditions in
when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical I
I
software in
max frequency to 50 MHz and updated other Internal SPI timing parameters to match names and
values from speed file in
period in
Updated selected I/O standard DC characteristics. Changed typical quiescent current temperature
from ambient to junction. Removed references to older software versions. Updated column 3 header
of
Table
Removed V
DIFF_SSTL18_II SSO limits in
software versions from
Spectrum
Table
Added I
leakage between pins of a differential pair. Added note 6 to
Time symbol in
Updated link to sign up for Alerts and updated
In
package and the XC3S1400AN in the FG(G)484 package.
CCAUXQ
Table
Table 17
25. Updated T
60.
IK
31, added the equivalent pairs per bank for the XC3S50AN and XC3S400AN in the FT(G)256
Table 17
quiescent current values by 12%-58% in
Table 51
to
section. Updated BPI configuration waveforms in
CCAUXT
Table
and
REF
Table
Table
Table
requirements for differential HSTL and differential SSTL in
19. Added reference to Sample Window in
since number of Read cycles is the only unique limit. Updated Setup, Hold, and
to match minimum frequency in
6. Updated V
and V
IOCKHZ
46. Corrected symbols for T
18. Added table note to
Table 47
Table 10
Table
CCO2T
www.xilinx.com
and T
Spartan-3AN FPGA Family: DC and Switching Characteristics
47. Restored Units column to
Table
POR minimum in
IN
and
and added reference to XAPP459, “Eliminating I/O Coupling Effects
IOCKON
in
1
Table 10
32. Updated table note 3 in
Table
of
Table
Table
synchronous output enable/disable times in
48. Added description of spread spectrum in
Revision
7,
32. Updated
and added a footnote to I
Table
Notice of
Table
Table 7
SUSPEND_GTS
Table
Table
18. Added T
8, and
12. Noted latest speed file v1.39 in ISE 10.1
Disclaimer.
52. Added references to User Guides.
and updated V
Software Version Requirements
Figure 17
Table
Table
Figure
Table
PEP
Figure
and T
Table
IOPI
for XC3S700AN in
49. Updated CCLK output maximum
13. Corrected CLK High and Low
24. Changed Internal SPI interface
17. Updated T
Table 23
13. Added V
and T
and
SUSPEND_GWE
39. Removed references to old
L
CCO
in
Table 59
IOPID
Table
Table 11
POR levels in
and
propagation times in
IN
30. Improved
ACC
Table
to show BPI data
to Recommended
Table
to note potential
in
Table
equation in
Table
25. Increased
CCINTQ
Spread
to note that
48.
Figure
28.
49.
and
13.
69

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