XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 71

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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DS557 (v4.1) April 1, 2011
Introduction
This section describes how the various pins on a Spartan®-3AN FPGA connect within the supported component packages,
and provides device-specific thermal characteristics. For general information on the pin functions and the package
characteristics, see the Packaging section of UG331:
Spartan-3AN FPGAs are available in Pb-free, RoHS packages, indicated by a “G” in the middle of the package code. Leaded
(Pb) packages are available for selected devices, with the same pinout and without the “G” in the ordering code (see
page
References to the Pb-free package code in this document apply also to the Pb package.
Pin Types
Most pins on a Spartan-3AN FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different
functional types of pins on Spartan-3AN FPGA packages, as outlined in
follow, the individual pins are color-coded according to pin type as in the table.
Table 62: Types of Pins on Spartan-3AN FPGAs
© Copyright 2007–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS557 (v4.1) April 1, 2011
Product Specification
Color Code
Type with
INPUT
VREF
DUAL
UG331: Spartan-3 Generation FPGA User Guide
http://www.xilinx.com/support/documentation/user_guides/ug331.pdf
CLK
I/O
7). The Pb-free package code can be selected in the software for the Pb packages since the pinouts are identical.
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential
I/Os.
Unrestricted, general-purpose input-only pin. This pin does not have an output structure,
differential termination resistor, or PCI™ clamp diode.
Dual-purpose pin used in some configuration modes during the configuration process and then
usually available as a user I/O after configuration. If the pin is not used during configuration, this
pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation Configuration User Guide for
additional information on these signals.
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other VREF pins
in the same bank, provides a reference voltage input for certain I/O standards. If used for a
reference voltage within a bank, all VREF pins within the bank must be connected.
Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 global
clock inputs that optionally clock the entire device. The exceptions are all devices in the TQG144
package and the XC3S50AN in the FTG256 package. The RHCLK inputs optionally clock the
right half of the device. The LHCLK inputs optionally clock the left half of the device. See the
Using Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for
additional information on these signals.
123
Description
www.xilinx.com
Table
Spartan-3AN FPGA Family:
62. In the package footprint drawings that
Pinout Descriptions
Product Specification
IO_#
IO_Lxxy_#
IP_#
IP_Lxxy_#
M[2:0]
PUDC_B
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
DOUT
CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
IP/VREF_#
IP_Lxx_#/VREF_#
IO/VREF_#
IO_Lxx_#/VREF_#
IO_Lxx_#/GCLK[15:0],
IO_Lxx_#/LHCLK[7:0],
IO_Lxx_#/RHCLK[7:0]
Pin Name(s) in
Type
(1)
Table 5,
71

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