SPARTAN-3A FPGA 1M 256-FTBGA

 

XC3S1000-5FTG256C

Manufacturer Part NumberXC3S1000-5FTG256C
DescriptionSPARTAN-3A FPGA 1M 256-FTBGA
ManufacturerXilinx Inc
SeriesSpartan™-3
XC3S1000-5FTG256C datasheets

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Specifications of XC3S1000-5FTG256C

Number Of Logic Elements/cells17280Number Of Labs/clbs1920
Total Ram Bits442368Number Of I /o173
Number Of Gates1000000Voltage - Supply1.14 V ~ 1.26 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case256-LBGAFor Use With122-1502 - KIT STARTER SPARTAN-3 PCI-E
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Spartan-3 FPGA Family: Pinout Descriptions
Revision History
Date
Version No.
04/03/03
1.0
Initial Xilinx release.
04/21/03
1.1
Added information on the VQ100 package footprint, including a complete pinout table
footprint diagram
final differential I/O pair counts for the TQ144 package. Added clarifying comments to HSWAP_EN pin
description on
Figure
Figure
column in
05/12/03
1.1.1
AM32 pin was missing GND label in FG1156 package diagram
07/11/03
1.1.2
Corrected misspellings of GCLK in
Dual-Purpose Pin I/O Standard During Configuration
XC3S5000 in FG1156 package, corrected N.C. symbol to a black square in
drawing.
07/29/03
1.2
Corrected pin names on FG1156 package. Some package balls incorrectly included LVDS pair names.
The affected balls on the FG1156 package include G1, G2, G33, G34, U9, U10, U25, U26, V9, V10, V25,
V26, AH1, AH2, AH33, AH34. The number of LVDS pairs is unaffected. Modified affected balls and
re-sorted rows in
electronic versions of FG1156 pinout.
08/19/03
1.2.1
Removed 100 MHz ConfigRate option in
note that TDO is a totem-pole output in
10/09/03
1.2.2
Some pins had incorrect bank designations and were improperly sorted in
functions changed. Renamed DCI_IN to DCI and added black diamond to N.C. pins in
Figure
12/17/03
1.3
Added FG320 pin tables and pinout diagram
cosmetic changes to the TQ144 footprint
footprint
the JTAG Port in 3.3V Environments
02/27/04
1.4
Clarified wording in
for FG320 and increased maximum I/O values for the FG676, FG900, and FG1156 packages.
07/13/04
1.5
Added information on lead-free (Pb-free) package options to the
Table 80
single termination as described in the
from Advance Product Specification to Product Specification.
08/24/04
1.5.1
Removed XC3S2000 references from
01/17/05
1.6
Added XC3S50 in CP132 package option. Added XC3S2000 in FG456 package option. Added
XC3S4000 in FG676 package option. Added
added
Table
105,
08/19/05
1.7
Removed term “weak” from the description of pull-up and pull-down resistors. Added
values. Added signal integrity precautions to
should be treated as an I/O during Master mode in
04/03/06
2.0
Added
Added detail about which pins have dedicated pull-up resistors during configuration, regardless of the
HSWAP_EN value to
When Using the JTAG Port in 3.3V
04/26/06
2.1
Corrected swapped data row in
Theta-JC column. Made additional notations on CONFIG and JTAG pins that have pull-up resistors
during configuration, regardless of the HSWAP_EN input.
216
Description
(Figure
42). Updated
Table 84
page
111. Updated the footprint diagram for the FG900 package shown in
50b. Some thick lines separating I/O banks were incorrect. Made cosmetic changes to
40, and
Figure
41. Updated Xilinx hypertext links. Added XC3S200 and XC3S400 to Pin Name
Table
90.
Table 68
and
Table
109. Updated affected balls in
CCLK: Configuration Clock
Table
76.
45, removed some extraneous text from pin 106 and corrected spelling of pins 45, 48, and 81.
(FG320: 320-lead Fine-pitch Ball Grid
(Figure
(Figure
49), and the FG900 footprint
(Figure
section.
Using JTAG Port After Configuration
and
Table
82. Clarified the VRN_# reference resistor requirements for I/O standards that use
DCI Termination Types
FG1156: 1156-lead Fine-pitch Ball Grid
Selecting the Right Package Option
Table
80,
Table
82,
Table
83,
Table
84,
Figure
43, and
Figure
49.
CCLK: Configuration Clock
Package Thermal
Characteristics. Updated
Table 69
and to
Pin Behavior During
Environments.
Table
85. The Theta-JA with zero airflow column was swapped with the
www.xilinx.com
with final I/O counts for the VQ100 package. Also added
(Figure
51).
Table
69. Changed CMOS25 to LVCMOS25 in
section. Clarified references to Module 2. For
Table
109, key, and package
Figure
51. Also updated ASCII and Excel
section and in
Table
92. No pin names or
44), the PQ208 footprint
(Figure
45), the FG676
50). Clarified wording in
Precautions When Using
section. In
Table
80, reduced package height
Package Overview
section and in
Figure
40b. Graduated
Array.
section. Modified or
Table
88,
Table
89,
Table
99,
Table
101,
IDCODE Register
and indicated that CCLK
Table
78.
Figure 39
to make it a more obvious example.
Configuration. Updated
DS099-4 (v2.5) December 4, 2009
Product Specification
R
(Table
86) and
Figure 50a
and
Figure
38,
Table
79. Added
Table
92. In
Array). Made
section plus
Table
102,
Precautions

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