SPARTAN-3A FPGA 1M 256-FTBGA

 

XC3S1000-5FTG256C

Manufacturer Part NumberXC3S1000-5FTG256C
DescriptionSPARTAN-3A FPGA 1M 256-FTBGA
ManufacturerXilinx Inc
SeriesSpartan™-3
XC3S1000-5FTG256C datasheets

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Specifications of XC3S1000-5FTG256C

Number Of Logic Elements/cells17280Number Of Labs/clbs1920
Total Ram Bits442368Number Of I /o173
Number Of Gates1000000Voltage - Supply1.14 V ~ 1.26 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case256-LBGAFor Use With122-1502 - KIT STARTER SPARTAN-3 PCI-E
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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S p ar t an -3 FP G A Fam ily : Fu n c t io n al D es c r ip t i o n
Configuration is automatically initiated after power-on
unless it is delayed by the user. INIT_B is an open-drain line
that the FPGA holds Low during the clearing of the configu-
ration memory. Extending the time that the pin is Low
causes the configuration sequencer to wait. Thus, configu-
ration is delayed by preventing entry into the phase where
data is loaded.
The configuration process can also be initiated by asserting
the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High. At this point, the con-
figuration data is written to the FPGA. The FPGA pulses the
Global Set/Reset (GSR) signal at the end of configuration,
resetting all flip-flops. The completion of the entire process
is signaled by the DONE pin going High.
Default Cycles
Start-Up Clock
Phase
0
1
2
3
DONE
GTS
GWE
Sync-to-DONE
Start-Up Clock
Phase
0
1
2
3
DONE High
DONE
GTS
GWE
Notes:
1.
The BitGen option StartupClk in the Xilinx
development software selects the CCLK input,
TCK input, or a user-designated clock input (via the
STARTUP_SPARTAN3 primitive) for receiving the
clock signal that synchronizes Start-Up.
Figure 29: Default Start-Up Sequence
The default start-up sequence, shown in
as a transition to the User mode. The default start-up
sequence is that one CCLK cycle after DONE goes High,
the Global Three-State signal (GTS) is released. This per-
mits device outputs to which signals have been assigned to
52
54
become active. One CCLK cycle later, the Global Write
Enable (GWE) signal is released. This permits the internal
storage elements to begin changing state in response to the
design logic and the user clock.
The relative timing of configuration events can be changed
via the BitGen options in the Xilinx development software. In
addition, the GTS and GWE events can be made depen-
dent on the DONE pins of multiple devices all going High,
forcing the devices to start synchronously. The sequence
can also be paused at any stage, until lock has been
achieved on any DCM.
Readback
Using Slave Parallel mode, configuration data from the
FPGA can be read back. Readback is supported only in the
Slave Parallel and Boundary-Scan modes.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed RAM, and block
RAM resources. This capability is used for real-time debug-
ging.
4
5
6 7
Additional Configuration Details
Additional details about the Spartan-3 FPGA configuration
architecture and command set are available in the “Spar-
tan-3 Generation Configuration User Guide” (
the "Spartan-3 Advanced Configuration Architecture" appli-
cation note (
Powering Spartan-3 FPGAs
Voltage Regulators
Various power supply manufacturers offer complete power
4
5
6 7
solutions for Xilinx FPGAs, including some with integrated
multi-rail regulators specifically designed for Spartan-3
FPGAs. The
vendor solution guides as well as Xilinx power estimation
and analysis tools.
Power Distribution System (PDS) Design and
Bypass/Decoupling Capacitors
Good power distribution system (PDS) design is important
for all FPGA designs, especially for high-performance appli-
DS099_028_060905
cations. Proper design results in better overall performance,
lower clock and DCM jitter, and a generally more robust sys-
tem. Before designing the printed circuit board (PCB) for the
FPGA design, review "Power Distribution System (PDS)
Design: Using Bypass/Decoupling Capacitors" (
Power-On Behavior
Spartan-3 FPGAs have a built-in Power-On Reset (POR)
Figure
29, serves
circuit that monitors the three power rails required to suc-
cessfully configure the FPGA. At power-up, the POR circuit
holds the FPGA in a reset state until the V
and V
CCO
www.xilinx.com
).
XAPP452
website provides links to
Xilinx Power Corner
CCINT
Bank 4 supplies reach their respective input
DS099-2 (v2.5) December 4, 2009
Product Specification
R
) and
UG332
).
XAPP623
, V
,
CCAUX

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