XC3S1000-5FTG256C | |
|---|---|
| Manufacturer Part Number | XC3S1000-5FTG256C |
| Description | SPARTAN-3A FPGA 1M 256-FTBGA |
| Manufacturer | Xilinx Inc |
| Series | Spartan™-3 |
| XC3S1000-5FTG256C datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
- We ship worldwide using main international couriers like FedEx, DHL, UPS, TNT, EMS. We can also use client's freight account. Other shipping methods can be discussed. We do best to meet your needs!
Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of XC3S1000-5FTG256C | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 17280 | Number Of Labs/clbs | 1920 |
| Total Ram Bits | 442368 | Number Of I /o | 173 |
| Number Of Gates | 1000000 | Voltage - Supply | 1.14 V ~ 1.26 V |
| Mounting Type | Surface Mount | Operating Temperature | 0°C ~ 85°C |
| Package / Case | 256-LBGA | For Use With | 122-1502 - KIT STARTER SPARTAN-3 PCI-E |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
PrevNext
R
Table 45: Timing for the IOB Three-State Path
Symbol
Description
Synchronous Output Enable/Disable Times
T
Time from the active transition at the
IOCKHZ
OTCLK input of the Three-state
Flip-Flop (TFF) to when the Output pin
enters the high-impedance state
(2)
T
Time from the active transition at TFF’s
IOCKON
OTCLK input to when the Output pin
drives valid data
Asynchronous Output Enable/Disable Times
T
Time from asserting the Global Three
GTS
State (GTS) net to when the Output pin
enters the high-impedance state
Set/Reset Times
T
Time from asserting TFF’s SR input to
IOSRHZ
when the Output pin enters a
high-impedance state
(2)
T
Time from asserting TFF’s SR input at
IOSRON
TFF to when the Output pin drives
valid data
Notes:
1.
The numbers in this table are tested using the methodology presented in
forth in
Table 31
and
Table
34.
2.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned
to the data Output. When this is true, add the appropriate Output adjustment from
3.
For minimums, use the values reported by the Xilinx timing analyzer.
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Spartan-3 FPGA Family: DC and Switching Characteristics
Conditions
LVCMOS25, 12mA
output drive, Fast slew
rate
LVCMOS25, 12mA
output drive, Fast slew
rate
LVCMOS25, 12mA
output drive, Fast slew
rate
Table 47
and are based on the operating conditions set
Table
www.xilinx.com
Speed Grade
-5
-4
Device
Max
Max
Units
All
0.74
0.85
ns
All
0.72
0.82
ns
XC3S200
7.71
8.87
ns
XC3S400
XC3S50
8.38
9.63
ns
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
All
1.55
1.78
ns
XC3S200
2.24
2.57
ns
XC3S400
XC3S50
2.91
3.34
ns
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
46.
73
Related parts for XC3S1000-5FTG256C | |||
|---|---|---|---|
| Part Number | Description | Manufacturer | Datasheet |
|
|
SPARTAN-3A FPGA 1M STD 256-FTBGA | Xilinx Inc | |
|
|
SPARTAN-3A FPGA 1M STD 456-FBGA | Xilinx Inc |
|
|
|
IC SPARTAN-3E FPGA 100K 144-TQFP | Xilinx Inc |
|
|
|
IC FPGA SPARTAN-3E 100K 144-TQFP | Xilinx Inc |
|
|
|
SPARTAN-3A FPGA 1M STD 676-FBGA | Xilinx Inc |
|
|
|
IC FPGA SPARTAN 3 256FTBGA | Xilinx Inc |
|
|
|
SEMI CONDUCTOR | Xilinx Inc |
|
|
|
FIELD PROGRAMMABLE GATE ARRAY | Xilinx Inc |
|
|
|
FIELD PROGRAMMER | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 256-Pin FTBGA | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 256-Pin FTBGA | Xilinx Inc |
|

