XCV100-6PQ240C

... XCV800 888,439 XCV1000 1,124,022 © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...

Virtex™ 2.5 V Field Programmable Gate Arrays Virtex Architecture Virtex devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) sur- rounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, ...

... Figure 1: Virtex Ordering Information www.xilinx.com 1-800-255-7778 Virtex™ 2.5 V Field Programmable Gate Arrays XCV400 XCV600 XCV800 166 166 166 316 316 316 404 404 404 404 444 444 512 512 = 0°C to +85° –40°C to +100°C) J XCV1000 404 512 Module ...

Virtex™ 2.5 V Field Programmable Gate Arrays Revision History Date Version 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1.4 Addition of package drawings and specifications. 05/99 ...

R DS003-2 (v2.8.1) December 9, 2002 Architectural Description Virtex Array The Virtex user-programmable gate array, shown in Figure 1, comprises two major configurable elements: con- figurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for ...

Virtex™ 2.5 V Field Programmable Gate Arrays TCE OCE CLK ICE Table 1: Supported Select I/O Standards I/O Standard LVTTL 2 – LVCMOS2 PCI PCI, 3.3 ...

R Input Path A buffer In the Virtex IOB input path routes the input signal either directly to internal logic or through an optional input flip-flop. An optional delay element at the D-input of this flip-flop elim- inates pad-to-pad hold ...

Virtex™ 2.5 V Field Programmable Gate Arrays more I/O pins convert to V pins. Since these are always REF a superset of the V pins used for smaller devices REF possible to design a PCB that permits migration ...

... Table 3 shows the amount of block SelectRAM memory that is available in each Virtex device. Table 3: Virtex Block SelectRAM Amounts Device XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 Routing, page 7. XCV1000 www.xilinx.com 1-800-255-7778 YB Y INIT REV INIT D ...

Virtex™ 2.5 V Field Programmable Gate Arrays Each block SelectRAM cell, as illustrated in fully synchronous dual-ported 4096-bit RAM with indepen- dent control signals for each port. The data widths of the two ports can be configured independently, providing built-in ...

R General Purpose Routing Most Virtex signals are routed on the general purpose rout- ing, and consequently, the majority of interconnect resources are associated with this level of the routing hier- archy. The general routing resources are located in horizon- ...

Virtex™ 2.5 V Field Programmable Gate Arrays Four dedicated clock pads are provided, one adjacent to each of the global buffers. The input to the global buffer is Global Clock Rows Delay-Locked Loop (DLL) Associated with each global clock input ...

R In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA, and also to read back the configuration data. Figure diagram of the Virtex Series boundary scan logic. It ...

... Virtex family the number of CLB rows (ranges from 010h for XCV50 to 040h for XCV1000 the company code (49h for Xilinx) The USERCODE register is supported. By using the USER- CODE, a user-programmable identification code can be loaded and shifted out for examination ...

R with a common user interface regardless of their choice of entry and verification tools. The XDM software simplifies the selection of implementation options with pull-down menus and on-line help. Application programs ranging from schematic capture to Placement and Routing ...

Virtex™ 2.5 V Field Programmable Gate Arrays Configuration Virtex devices are configured by loading configuration data into the internal configuration memory. Some of the pins used for this are dedicated configuration pins, while others can be re-used as general purpose ...

R Table 8: Master/Slave Serial Mode Programming Switching Description DIN setup/hold, slave mode DIN setup/hold, master mode DOUT High time CCLK Low time Maximum Frequency Frequency Tolerance, master mode with respect to nominal MASTER Optional Pull-up 1 ...

Virtex™ 2.5 V Field Programmable Gate Arrays Master-Serial Mode In master-serial mode, the CCLK output of the FPGA drives a Xilinx Serial PROM that feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK ...

R FPGA starts to clear configuration memory. FPGA makes a final clearing pass and releases Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error CRC errors found, FPGA enters start-up phase causing DONE ...

Virtex™ 2.5 V Field Programmable Gate Arrays 3. At the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High (from a previous write), the data is not accepted. Acceptance will ...

R FPGA starts to clear configuration memory. FPGA makes a final clearing pass and releases Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error. first FPGAs enter start-up phase later FPGAs enter start-up phase When ...

Virtex™ 2.5 V Field Programmable Gate Arrays CCLK CS WRITE DATA[0:7] BUSY Figure 18: SelectMAP Write Abort Waveforms Boundary-Scan Mode In the boundary-scan mode, configuration is done through the IEEE 1149.1 Test Access Port. Note that the PROGRAM pin must ...

... Configuration Bits XCV50 XCV100 XCV150 1,040,096 XCV200 1,335,840 XCV300 1,751,808 XCV400 2,546,048 XCV600 3,607,968 XCV800 4,715,616 XCV1000 6,127,744 Revision History Date Version 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1 ...

Virtex™ 2.5 V Field Programmable Gate Arrays Date Version 01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. 03/00 2.0 New ...

... Speed Grade Designations Device Advance XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 All specifications are subject to change without notice. www.xilinx.com 1-800-255-7778 Preliminary Production –6, –5, –4 –6, –5, –4 –6, –5, –4 –6, –5, –4 –6, –5, –4 –6, –5, –4 – ...

Virtex™ 2.5 V Field Programmable Gate Arrays Virtex DC Characteristics Absolute Maximum Ratings Symbol V Supply voltage relative to GND CCINT V Supply voltage relative to GND CCO V Input Reference Voltage REF Input voltage relative to GND V IN ...

... Virtex™ 2.5 V Field Programmable Gate Arrays Device Min Max All 2.0 All 1.2 XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 100 XCV800 100 XCV1000 100 XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 All All –10 +10 All All 0.25 Note (2) Note (2) 0.15 Units ...

Virtex™ 2.5 V Field Programmable Gate Arrays Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual current consumed depends on the power-on ramp rate of the power ...

... IOPID XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 All T IOPLI XCV50 T IOPLID XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 All IOCKIQ www.xilinx.com 1-800-255-7778 Virtex™ 2.5 V Field Programmable Gate Arrays Speed Grade Min - 0.39 0.8 0.9 1.0 0.8 1.5 1 ...

... Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Module Device Symbol All T /T IOPICK IOICKP XCV50 T /T IOPICKD IOICKPD XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 All T /T IOICECK IOCKICE All T IOSRCKI All T IOSRIQ All T GSRQ Table www.xilinx.com 1-800-255-7778 Speed Grade Min -6 -5 ...

R IOB Input Switching Characteristics Standard Adjustments Description Data Input Delay Adjustments Standard-specific data input delay adjustments Notes: 1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see IOB Output Switching Characteristics Output delays terminating ...

Virtex™ 2.5 V Field Programmable Gate Arrays Description Clock CLK to Pad delay with OBUFT enabled (non-3-state) Clock CLK to Pad high-impedance (1) (synchronous) Clock CLK to valid data on Pad delay, plus enable delay for OBUFT Setup and Hold ...

R IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Description Output Delay Adjustments Standard-specific ...

Virtex™ 2.5 V Field Programmable Gate Arrays Calculation Function of ioop Capacitance T is the propagation delay from the O Input of the IOB to ioop the pad. The values for T were based on the ...

... Virtex™ 2.5 V Field Programmable Gate Arrays Device Symbol -6 XCV50 T 0.10 GSKEWIOB XCV100 0.12 XCV150 0.12 XCV200 0.13 XCV300 0.14 XCV400 0.13 XCV600 0.14 XCV800 0.16 XCV1000 0.20 Speed Grade Symbol Min -6 T 0.33 0.7 GPIO T 0.34 0.7 GIO www.xilinx.com 1-800-255-7778 Speed Grade -5 -4 Units 0.12 0.14 ns, max 0 ...

Virtex™ 2.5 V Field Programmable Gate Arrays I/O Standard Global Clock Input Adjustments Description Data Input Delay Adjustments Standard-specific global clock input delay adjustments Notes: 1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see ...

R CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Description Combinatorial Delays 4-input function: F/G inputs to X/Y outputs ...

Virtex™ 2.5 V Field Programmable Gate Arrays CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Description Combinatorial ...

R CLB SelectRAM Switching Characteristics Description Sequential Delays Clock CLK to X/Y outputs (WE active mode Clock CLK to X/Y outputs (WE active mode Shift-Register Mode Clock CLK to X/Y outputs Setup and Hold ...

Virtex™ 2.5 V Field Programmable Gate Arrays Block RAM Switching Characteristics Description Sequential Delays Clock CLK to DOUT output Setup and Hold Times before/after Clock CLK ADDR inputs DIN inputs EN input RST input WEN input Clock CLK Minimum Pulse ...

... Table 3. Symbol Device Min T XCV50 1.5 ICKOF XCV100 1.5 XCV150 1.5 XCV200 1.5 XCV300 1.5 XCV400 1.5 XCV600 1.6 XCV800 1.6 XCV1000 1.7 Table 2 and Table 3. www.xilinx.com 1-800-255-7778 Speed Grade - Units 3.1 3.3 3.6 ns, max 3.1 3.3 3.6 ns, max 3.1 3.3 3 ...

Virtex™ 2.5 V Field Programmable Gate Arrays Minimum Clock-to-Out for Virtex Devices With DLL I/O Standard All Devices *LVTTL_S2 5.2 *LVTTL_S4 3.5 *LVTTL_S6 2.8 *LVTTL_S8 2.2 *LVTTL_S12 2.0 *LVTTL_S16 1.9 *LVTTL_S24 1.8 *LVTTL_F2 2.9 *LVTTL_F4 1.7 *LVTTL_F6 1.2 *LVTTL_F8 1.1 ...

... XCV150 0.40 /–0.4 XCV200 0.40 /–0.4 XCV300 0.40 /–0.4 XCV400 0.40 /–0.4 XCV600 0.40 /–0.4 XCV800 0.40 /–0.4 XCV1000 0.40 /–0.4 www.xilinx.com 1-800-255-7778 Virtex™ 2.5 V Field Programmable Gate Arrays Speed Grade - 1.7 /–0.4 1.8 /–0.4 2.1 /–0.4 1.7 /–0.4 1.9 /– ...

... Module Symbol Device Min T /T XCV50 0 PSFD PHFD XCV100 0 XCV150 0 XCV200 0 XCV300 0 XCV400 0 XCV600 0 XCV800 0 XCV1000 0 www.xilinx.com 1-800-255-7778 Speed Grade - Units (2) For data input with different ...

R DLL Timing Parameters All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating ...

Virtex™ 2.5 V Field Programmable Gate Arrays Period Tolerance: the allowed input clock period change in nanoseconds. T CLKIN Output Jitter: the difference between an ideal reference clock edge and the actual design. Ideal Period Actual Period Revision History Date ...

R Date Version 01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. 03/00 2.0 New TBCKO values; corrected FG680 package connection ...

Virtex™ 2.5 V Field Programmable Gate Arrays Module www.xilinx.com 1-800-255-7778 R DS003-3 (v3.2) September 10, 2002 Production Product Specification ...

R DS003-4 (v2.8) July 19, 2002 Virtex Pin Definitions Table 1: Special Purpose Pins Dedicated Pin Name Pin GCK0, GCK1, Yes GCK2, GCK3 M0, M1, M2 Yes CCLK Yes PROGRAM Yes DONE Yes INIT No BUSY/ No DOUT D0/DIN, No ...

Virtex™ 2.5 V Field Programmable Gate Arrays Virtex Pinout Information Pinout Tables See for updates or additional pinout information. For convenience, www.xilinx.com locations of special-purpose and power-supply pins. Pins not listed are either user I/Os or not connected, depending on ...

... V pins are general REF I/ Bank 2 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device XCV400 and all smaller devices XCV600 listed in the same package.) XCV800 Within each bank, if ...

... V pins are general REF I/ Bank 5 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device XCV400 and all smaller devices XCV600 listed in the same package.) XCV800 Within each bank, if ...

... V pins are general REF I/ Bank 7 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device XCV400 and all smaller devices XCV600 listed in the same package.) XCV800 Within each bank, if ...

Virtex™ 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) Pin Name GCK0 GCK1 GCK2 GCK3 CCLK PROGRAM DONE INIT BUSY/DOUT D0/DIN WRITE CS TDI TDO TMS ...

R Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name V CCINT Notes: • Superset includes all pins, including the ones in bold type. Subset excludes pins in bold type. • In BG352, for XCV300 all the V pins in ...

... N/A XCV50 A17, B12 XCV100/150 ... + B15 XCV200/300 ... + B17 XCV400 N/A XCV600 N/A XCV800 N/A XCV1000 N/A XCV50 C20, J18 XCV100/150 ... + F19 XCV200/300 ... + G18 XCV400 N/A XCV600 N/A XCV800 N/A XCV1000 N/A www.xilinx.com 1-800-255-7778 BG352 BG432 A31, L28, L31 C32, D33, K33, ...

... N/A XCV600 N/A XCV800 N/A XCV1000 N/A XCV50 V9, Y3 XCV100/150 ... + W6 AC15, AC18, XCV200/300 ... + V7 ... + AE23 XCV400 N/A XCV600 N/A XCV800 N/A XCV1000 N/A XCV50 M2, R3 XCV100/150 ... + T1 R24, Y26, XCV200/300 ... + T3 ... + AD26 XCV400 N/A XCV600 N/A XCV800 N/A XCV1000 N/A www.xilinx.com 1-800-255-7778 BG352 BG432 ...

... Module Device BG256 XCV50 G3, H1 XCV100/150 ... + D1 D26, G26, XCV200/300 ... + B2 ... + E24 XCV400 N/A XCV600 N/A XCV800 N/A XCV1000 N/A All C3, C18, A1, A2, A5, D4, D5, A8, A14, D9, D10, A19, A22, D11, A25, A26, D12, B1, B26, E1, D16, E26, H1, D17, E4, H26, N1, E17, J4, P26, W1, ...

R Table 4: Virtex Pinout Tables (Fine-Pitch BGA) Pin Name Device GCK0 GCK1 GCK2 GCK3 CCLK PROGRAM DONE INIT BUSY/DOUT D0/DIN WRITE CS TDI TDO TMS TCK DXN DXP DS003-4 ...

... XCV400 all smaller devices listed in the same XCV600 package.) Within each bank, if XCV800 input reference voltage is not required, all V REF XCV1000 pins are general I/O. Module FG256 FG456 All C3, C14, D4, E5, E18, F6, D13, E5, F17, G7, G8, G9, E12, M5, ...

... V REF XCV1000 pins are general I/ Bank 3 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device and XCV400 all smaller devices listed in the same XCV600 package.) Within each bank, if ...

... XCV800 is not required, all V REF pins are general I/O. XCV1000 V , Bank 6 XCV50 REF (V pins are listed XCV100/150 REF incrementally. Connect XCV200/300 all pins listed for both the required device and XCV400 all smaller devices listed in the same XCV600 package.) Within each bank, if ...

... XCV400 all smaller devices listed in the same XCV600 package.) Within each bank, if XCV800 input reference voltage is not required, all V REF XCV1000 pins are general I/O. GND DS003-4 (v2.8) July 19, 2002 Production Product Specification FG256 FG456 C1, H3 ... + D1 E2, H4, K3 ... + B1 ...

Virtex™ 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name Device No Connect XCV800 (No-connect pins are listed incrementally. All pins listed for both the required device and all larger devices listed in ...

R Pinout Diagrams The following diagrams, CS144 Pin Function page 17 through FG680 Pin Function illustrate the locations of special-purpose pins on Virtex FPGAs. Table 5 lists the symbols used in these diagrams. The diagrams also show I/O-bank boundaries. Table ...

Virtex™ 2.5 V Field Programmable Gate Arrays TQ144 Pin Function Diagram ✳ ✳ ✳ ✳ 3 ✳ ✳ ✳ Bank 0 ✳ ...

R PQ240/HQ240 Pin Function Diagram ✳ ✳ ✳ ✳ ✳ ✳ ✳ 7 ✳ ✳ ✳ Bank 7 V ...

Virtex™ 2.5 V Field Programmable Gate Arrays BG256 Pin Function Diagram A ✳ r ✳ B ✳ ✳ ✳ ✳ ✳ E ✳ ✳ ✳ F ✳ ✳ ✳ ✳ ✳ J ✳ ✳ ✳ K ...

R BG352 Pin Function Diagram ✳ ✳ ✳ ✳ ➉ ✳ ✳ ✳ ✳ F ➀ ✳ ✳ G ✳ ✳ ✳ ➁ ...

Virtex™ 2.5 V Field Programmable Gate Arrays BG432 Pin Function Diagram ✳ ✳ ✳ ✳ ✳ ➉ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ...

R BG560 Pin Function Diagram ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ...

Virtex™ 2.5 V Field Programmable Gate Arrays FG256 Pin Function Diagram Bank Bank Module Bank 0 Bank 1 ...

R FG456 Pin Function Diagram G ❅ ✳ ✳ ✳ A ✳ B ✳ ❅ C ❅ Bank 7 D ✳ E ✳ ✳ ✳ ✳ ✳ F ✳ ❅ ✳ ✳ ✳ G ✳ ✳ ✳ H ❅ ✳ ...

Virtex™ 2.5 V Field Programmable Gate Arrays FG676 Pin Function Diagram ✳ ✳ ✳ ✳ ✳ ❄ ❄ ✳ R ❄ ❄ r ✳ ✳ ✳ ✳ ✳ ✳ ❄ ...

R FG680 Pin Function Diagram Bank ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ 3 ✳ ✳ ✳ ✳ ✳ r ✳ ✳ ✳ ✳ ✳ ✳ R ...

Virtex™ 2.5 V Field Programmable Gate Arrays Revision History Date Version 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1.4 Addition of package drawings and specifications. 05/99 ...