XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all test-
ing. (See
Virtex-II Pro Platform FPGA User Guide
details.) The propagation delay of the 4" trace is character-
ized separately and subtracted from the final measurement,
and is therefore not included in the generalized test setup
shown in
Figure
6.
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. (IBIS
models can be found on the web at
inx.com/support/sw_ibis.htm
.) Parameters V
C
, and V
fully describe the test conditions for each
REF
MEAS
I/O standard. The most accurate prediction of propagation
delay in any given application can be obtained through IBIS
simulation, using the following method:
1. Simulate the output driver of choice into the generalized
test setup, using values from
Table
2. Record the time to V
.
MEAS
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
Table 37: Output Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS ), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
DS083 (v4.7) November 5, 2007
Product Specification
4. Record the time to V
5. Compare the results of steps 2 and 4. The increase or
decrease in delay should be added to or subtracted
from the I/O Output Standard Adjustment value
(Table
35) to yield the actual worst-case propagation
for
delay (clock-to-input) of the PCB trace.
FPGA Output
http://support.xil-
, R
,
REF
REF
37.
IOSTANDARD
Attribute
LVTTL (all)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3 (rising edge)
PCI33_3 (falling edge)
PCI66_3 (rising edge)
PCI66_3 (falling edge)
PCIX (rising edge)
PCIX (falling edge
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III_18
HSTL_IV_18
www.xilinx.com
.
MEAS
V
REF
R
REF
V
MEAS
(voltage level at which
delay measurement is taken)
C
REF
(probe capacitance)
ds083-3_06a_092503
Figure 6: Generalized Test Setup
(1)
R
C
V
REF
REF
MEAS
(Ω)
(pF)
(V)
1M
0
1.65
1M
0
1.65
1M
0
1.25
1M
0
0.9
1M
0
0.75
(2)
25
10
0.94
(2)
25
10
2.03
(2)
25
10
0.94
(2)
25
10
2.03
(3)
25
10
0.94
(3)
25
10
2.03
25
0
0.8
25
0
1.0
50
0
V
REF
25
0
V
REF
50
0
0.9
25
0
0.9
50
0
V
REF
25
0
V
REF
50
0
1.1
25
0
1.1
Module 3 of 4
V
REF
(V)
0
0
0
0
0
0
3.3
0
3.3
0
3.3
1.2
1.5
0.75
0.75
1.5
1.5
0.9
0.9
1.8
1.8
30