XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Configuration Timing
Configuration Memory Clearing Parameters
Power-up timing of configuration signals is shown in
V
CC
PROG_B
INIT_B
CCLK
(Output
or Input)
M0, M1, M2*
(Required)
Table 46: Power-Up Timing Characteristics
Description
Power-on reset
Program latency
CCLK (output) delay
Program pulse width
Notes:
1. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied
directly to ground or V
. The mode pins should not be toggled during and after configuration.
CCAUX
DS083 (v4.7) November 5, 2007
Product Specification
Figure
7; corresponding timing characteristics are listed in
T
1
POR
T
2
PL
*Can be either 0 or 1, but must not toggle during and after configuration.
Figure 7: Configuration Power-Up Timing
Figure
References
Symbol
1
T
POR
2
T
PL
3
T
ICCK
T
PROGRAM
www.xilinx.com
Table
3
T
ICCK
ds083-3_07_012004
Value
Units
T
+ 2
ms, max
PL
μ
4
s per frame, max
μ
0.25
s, min
μ
4.00
s, max
300
ns, min
Module 3 of 4
46.
37