XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 113

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
Without DCM
Table 51: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
Without DCM
Description
LVCMOS25 Global Clock Input to Output
Delay using Output Flip-flop, 12 mA, Fast
Slew Rate, without DCM.
For data output with different standards,
adjust the delays with the values shown in
IOB Output Switching Characteristics
Standard Adjustments, page
26.
Global Clock and OFF without DCM
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% V
3. DCM output jitter is already included in the timing calculation.
DS083 (v4.7) November 5, 2007
Product Specification
Symbol
Device
T
XC2VP2
ICKOF
XC2VP4
XC2VP7
XC2VP20
XC2VPX20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VPX70
XC2VP100
threshold with test setup shown in
Figure
CC
www.xilinx.com
Speed Grade
-5
-7
-6
3.19
3.52
3.82
3.39
3.91
4.27
3.59
4.00
4.36
3.62
4.08
4.46
3.62
4.08
4.46
3.73
4.12
4.50
3.89
4.28
4.67
4.00
4.43
4.84
4.38
4.87
5.33
4.38
4.87
5.33
N/A
5.32
5.82
6. For other I/O standards, see
Table
37.
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
42

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