XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 122

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 64: Example Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
Description
Example Data Input Set-Up and Hold Times
Relative to a Forwarded Clock Input Pin,
Using DCM and Global Clock Buffer.
Values represent an 18-bit bus located in Banks
2, 3, 6, or 7 and grouped to one Horizontal
Global Clock Line. TRACE must be used to
determine the actual values for any given
design.
For situations where clock and data inputs
conform to different standards, adjust the setup
and hold values accordingly using the values
shown in
IOB Input Switching Characteristics
Standard Adjustments, page
23.
No Delay
(2)
Global Clock and IFF
with DCM
Notes:
1. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include:
-
CLK0 and CLK180 DCM jitter
-
Worst-case duty-cycle distortion using CLK0 and CLK180, T
Package skew is not included in these measurements.
2. IFF = Input Flip-Flop
Source Synchronous Timing Budgets
This section describes how to use the parameters provided
in the
Source-Synchronous Switching Characteristics
tion to develop system-specific timing budgets. The follow-
ing analysis provides information necessary for determining
Virtex-II Pro contributions to an overall system timing analy-
sis; no assumptions are made about the effects of
Inter-Symbol Interference or PCB skew.
Virtex-II Pro Transmitter Data-Valid Window (T
T
is the minimum aggregate valid data period for a
X
source-synchronous data bus at the pins of the device and
is calculated as follows:
(1)
T
= Data Period - [Jitter
+ Duty Cycle Distortion
X
(3)
(4)
TCKSKEW
+ TPKGSKEW
DS083 (v4.7) November 5, 2007
Product Specification
Symbol
(1)
T
/T
PSDCM_0
PHDCM_0
XC2VP20
XC2VPX20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VPX70
XC2VP100
DCD_CLK180
Notes:
1. Jitter values and accumulation methodology to be provided in
sec-
a future release of this document. The absolute period jitter
values found in the
particular DCM output clock used to clock the IOB FF can be
used for a best case analysis.
2. This value depends on the clocking methodology used. See
Note1 for
3. This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
)
X
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
4. These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time
(2)
+
from Pad to Ball.
]
www.xilinx.com
Speed Grade
Device
7
6
XC2VP2
0.23/0.39
0.21/0.42
0.21/0.42
XC2VP4
0.26/0.37
0.24/0.40
0.24/0.41
XC2VP7
0.18/ 0.36
0.18/ 0.40
0.18/ 0.41
0.14/ 0.41
0.13/ 0.42
0.12/ 0.44
0.14/ 0.41
0.13/ 0.42
0.12/ 0.44
0.29/ 0.25
0.31/ 0.24
0.31/ 0.24
0.25/ 0.30
0.26/ 0.29
0.27/ 0.29
0.18/ 0.36
0.18/ 0.38
0.17/ 0.39
0.18/ 0.37
0.18/ 0.38
0.18/ 0.38
0.18/ 0.37
0.18/ 0.38
0.18/ 0.38
N/A
0.18/ 0.33
0.19/ 0.37
DCM Timing Parameters
Table 61
.
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
section of the
Module 3 of 4
51

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