XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
Page 121
122
Page 122
123
Page 123
124
Page 124
125
Page 125
126
Page 126
127
Page 127
128
Page 128
129
Page 129
130
Page 130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
Page 123/430

Download datasheet (4Mb)Embed
PrevNext
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Virtex-II Pro Receiver Data-Valid Window (R
R
is the required minimum aggregate valid data period for
X
a source-synchronous data bus at the pins of the device
and is calculated as follows:
(1)
(2)
R
= [TSAMP
+ TCKSKEW
X
Notes:
1. This parameter indicates the total sampling error of
Virtex-II Pro DDR input registers across voltage, temperature,
and process. The characterization methodology uses the DCM
to capture the DDR input registers’ edges of operation. These
measurements include:
-
CLK0 and CLK180 DCM jitter in a quiet system
Revision History
This section records the change history for this module of the data sheet.
Date
Version
01/31/02
1.0
Initial Xilinx release.
06/17/02
2.0
09/03/02
2.1
09/27/02
2.2
Added section
11/20/02
2.3
Updated parametric information in:
11/25/02
2.4
Table
DS083 (v4.7) November 5, 2007
Product Specification
)
-
X
-
-
These measurements do not include package or clock tree
skew.
(3)
+ TPKGSKEW
]
2. This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
3. These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
Added new Virtex-II Pro family members.
Added timing parameters from speedsfile v1.62.
Added
Table
43,
Pipelined Multiplier Switching
Added 3.3V-vs-2.5V table entries for some parameters.
Added
Source-Synchronous Switching Characteristics
Added absolute max ratings for 3.3V-vs-2.5V parameters in
Added recommended operating conditions for V
Updated SSTL2 values in
Table
6. Added SSTL18 values:
[Table 32
removed in v2.8.]
Added
Table
10, which contains LVPECL DC specifications.
General Power Supply
Requirements.
Table
1: Increase Absolute Max Rating for V
3.75V. Delete cautionary footnotes related to voltage overshoot/undershoot.
Table
2: Delete V
specifications for 2.5V and below operation. Delete footnote
CCO
referencing special information for 3.3V operation. Add footnote for PCI/PCI-X.
Table
3: Add I
. Delete I
specifications for 2.5V and below operation.
BATT
L
Table
4: Add Typical Quiescent Supply Currents for XC2VP4 and XC2VP7 only
Table
6: Correct I
and I
for SSTL2 I. Add rows for LVTTL, LVCMOS33, and PCI-X.
OL
OH
Correct max V
from V
to 3.6V.
IH
CCO
Table
7: Correct Min/Max V
, V
OD
OCM
Table
10: Reformat LVPECL DC Specifications to match Virtex-II data sheet format
Table
12: Correct parameter name from Differential Output Voltage to Single-Ended
Output Voltage Swing.
Table
16: Add CPMC405CLOCK max frequencies
Table
27: Add footnote regarding serial data rate limitation in -5 part.
Table
36: Add rows for LVTTL, LVCMOS33, and PCI-X.
Table
32: Add LVTTL, LVCMOS33, and PCI-X. Correct all capacitive load values
(except PCI/PCI-X) to 0 pF.
[Table 32
Table
48: Correct CCLK max frequencies
1: Correct lower limit of voltage range of V
www.xilinx.com
Worst-case duty-cycle distortion
DCM accuracy (phase offset)
DCM phase shift resolution.
Revision
Characteristics.
section.
Table
1.
and RocketIO footnote to
IN
Table
6,
Table
, V
, V
, and V
from 3.6V to
CCO
REF
IN
TS
, and V
ICM
removed in v2.8.]
and V
from –0.3V to –0.5V for 3.3V.
IN
TS
Table
2.
36,
Table
32.
Module 3 of 4
52