XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Date
Version
12/03/02
2.5
Updated parametric information in:
01/20/03
2.6
Updated parametric information in:
03/24/03
2.7
05/27/03
2.8
05/27/03
2.8
(cont’d)
(cont’d)
DS083 (v4.7) November 5, 2007
Product Specification
Table
1: Correct lower limit of voltage range of V
3.3V.
Table
2: Add footnote (2) regarding V
Table
12: Add waveform diagrams
(Figure 1
(differential).
(single-ended) and DV
PPOUT
Table
23: Indicate REFCLK upper frequency limitation; relate REFCLK parameters to
REFCLK2, BREFCLK, and BREFCLK2; correct T
measurement.
Table
57: Add qualifying footnote to CLKOUT_DUTY_CYCLE_DLL
Table
12: Correct DV
Min (200 mV to 175 mV) and DV
IN
Table
23: Correct T
/T
Typ (400 ps to 600 ps) and Max (600 ps to 1000 ps).
RCLK
FCLK
Add footnote (2) to qualify Max T
GJTT
Table
56: Correct hyperlink in footnote (1) to point directly to Answer Record 13645.
Move clock parameters from
Table
Added/updated timing parameters from speedsfile v1.76.
Table
2: Delete first table footnote and renumber all others.
Table
3: Add "sample-tested" to I
. Remove "Device" column, unnecessary.
L
Table
8: Update V
(Typ) to 1.250V.
OCM
Table
10: Update LVPECL_25 DC parameters.
Table
23: Update F
frequency ranges. Break out T
GCLK
Table
27: Update F
frequency ranges. Correct T
GTX
Table
36: Update V
(Typ) for HSTL Class I/II from 1.08V to 0.90V.
REF
Table
40,
Table
41: Correct parameter name "CE input (WS)" to "SR input".
Table
61: Break out T
by device type.
DCD_CLK0
Updated time and frequency parameters as per speedsfile v1.78.
Table
3: Added values for I
, I
, I
REF
L
RPU
Corrected I
(Table
4) and I
CCINTQ
CCINTMIN
Table
4: Updated/Added Typ and Max quiescent current values for XC2VP7 and
XC2VP20. Added footnote specifying parameters are for Commercial Grade parts.
Table
5: Added footnote specifying parameters are for Commercial Grade parts.
Table
6: Corrected V
(Max) for LVTTL and LVCMOS33 standards from 3.6V to 3.45V.
IH
Changed V
(Min) for all standards to –0.2V. Corrected V
IL
LVCMOS18 from 20% V
to 30% V
CCO
Table
10: Corrected LVPECL_25 Min and Max values for V
explanatory text above table.
Table 13
and
Table 14
(pin-pin and reg-reg performance): Changed device specified
from XC2VP7FF672-6 to XC2VP20FF1152-6.
Table
15: Updated to show devices XC2VP7 and XC2VP20 as Preliminary for the -6
speed grade and Production for the -5 speed grade.
Removed former Table 32, Standard Capacitive Loads.
Table
49: Updated T
from 4.0 ns to 5.5 ns.
TAPTCK
Table
56: Modified footnote referenced at CLKFX/CLKFX180 to point to the online
Jitter Calculator.
Added
Figure 6
and accompanying procedure for measuring standard adjustments.
Table
1: Footnote (2) rewritten to specify “one or more banks.”
Table
54: Some DCM parameters were erroneously missing from v2.8 (single-module
version) due to a document compilation error. The concatenated full data sheet version
was not affected. These parameters have been restored.
www.xilinx.com
Revision
and V
from –0.5V to –0.3V for
IN
TS
voltage droop. Renumbered other notes.
CCAUX
and
Figure
2) illustrating DV
and T
values and unit of
RCLK
FCLK
.
Max (1000 mV to 2000 mV).
IN
parameter.
18,
Table
19,
Table
20, and
Table 21
by operating speed.
GJTT
to 0.17 UI, T
to o.18 UI.
DJ
RJ
, I
RPD
(Table
5) for XC2VP20 to 600 mA.
(Max) for LVCMOS15 and
IL
.
CCO
and V
. Added
IH
IL
OUT
to
Table
16.
Module 3 of 4
53