XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 125

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Date
Version
08/25/03
2.9
09/10/03
2.10
10/14/03
2.11
11/10/03
2.12
12/05/03
3.0
DS083 (v4.7) November 5, 2007
Product Specification
Updated time and frequency parameters as per speedsfile v1.81.
Table
1: Footnote (2) rewritten to specify “one or more banks.”
Table
2: Added footnote referring to XAPP659 for 3.3V I/O operation.
Table 50
and
Table
51: Revised test setup footnote to refer to
specified a capacitive load parameter.
Table
54: Due to a document compilation error in v2.8, some DCM parameters were
erroneously omitted from the full data sheet file (all four modules concatenated),
though not from the stand-alone Module 3 file. The omitted parameters have been
restored.
Table 61
and
Table
63: Corrected parameters to expression in picoseconds, as
labeled. Previously expressed in nanoseconds, but labeled picoseconds.
Figure 6: Added note to figure regarding termination resistors.
Table
5: Added I
for XC2VP30 device.
CCINTMIN
Figure
7: Changed representation of mode pins M0, M1, and M2 indicating that they
must be held to a constant DC level during and after configuration.
Table
46: Added footnote indicating that mode pins M0, M1, and M2 must be held to a
constant DC level during and after configuration.
Table
1: Deleted Footnote (2), which had derated the absolute maximum T
or more banks operated at 3.3V. Changed T
temperature” to “Maximum junction temperature”. Added new Footnote (2) linking to
website for package thermal data.
Table 4
and
Table
5: Filled in power-on and quiescent current parameters for all
devices through XC2VP70. Added Industrial Grade multiplier specification to Footnote
(1) in both tables.
In section
General Power Supply
Requirements, replaced reference to Answer Record
11713 with reference to
regarding handling of simultaneously switching
XAPP689
outputs (SSO).
In section
I/O Standard Adjustment Measurement
-
Table 36
renamed
Input Delay Measurement
-
Added new
Table
37,
Output Delay Measurement
-
Replaced
Figure
6,
Generalized Test
-
Revised and extended text describing output delay measurement procedure.
Table
55: For Input Clock Low/High Pulse Width, PSCLK and CLKIN, changed existing
Footnote (2) to new Footnote (3).
Table
1: Changed 3.3V absolute max V
footnote referring to
XAPP659
.
Table
4: Removed MIN column from table.
XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades
-5 and -6, updated and released to Production status as per speedsfile v1.83.
Featured changes:
-
Speedsfile parameter values for -7 speed grade added for devices
XC2VP2-XC2VP70.
-
Table 13
and
Table
14: Pin-to-pin and register-to_register performance parameter
values added.
-
Table
61: New parameter T
DCD_LOCAL
-
All remaining source-synchronous parameter values added
www.xilinx.com
Revision
Figure
6. Previously
description from “Operating junction
J
Methodology:
Methodology. Added footnotes.
Methodology.
Setup, with new drawing.
and V
from 3.75V to 4.05V. Added
IN
TS
(and footnote) replaces T
DCD_CLK0
(Table 61
when one
J
.
& following).
Module 3 of 4
54

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