XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Date
Version
12/05/03
3.0
(cont’d)
(cont’d)
02/19/04
3.1
03/09/04
3.1.1
04/22/04
3.2
06/30/04
4.0
Merged in DS110-3 (Module 3 of Virtex-II Pro X data sheet). This merge added numerous
previously unpublished RocketIO X MGT parameters. Specifications in this revision are
from speedsfile v1.86.
DS083 (v4.7) November 5, 2007
Product Specification
Non-speedsfile parameter values added or updated:
Table
3: I
.
BATT
Table
4: For XC2VP100, I
, I
CCINTQ
CCOQ
Table
5: For XC2VP100, I
.
CCINTMIN
Table
17: T
and T
.
CPWL
CPWH
Table
25: Added explanatory footnote to T
Table
54: Added Footnote (3) regarding use of CLKIN_DIVIDE_BY_2 attribute.
Updated time and frequency parameters as per speedsfile v1.85.
Table
2,
Recommended Operating
Table
4,
Quiescent Supply
Current: Added Footnote (1) and updated Typical
parameters.
Table
10,
LVPECL DC
Specifications: Added parameter values for Maximum
Differential Input Voltage (LVPECL).
Table
14,
Register-to-Register
Performance: Removed reference to a number of
designs for which test data is no longer provided.
Table
16,
Processor Clocks Absolute AC
to XAPP755.
Added
Table
38,
Clock Distribution Switching
Revised section
Configuration Timing, page 37
Access Port Switching Characteristics, page
parameter tables, and organization.
Table
47,
Master/Slave Serial Mode Timing
Mode Write Timing
Characteristics: Added parameter F
Table
48,
SelectMAP Mode Write Timing
DATA[0:7] setup/hold time, by device, and added new parameter specifications for
XC2VP70 and XC2VP100 devices.
Table
54,
Operating Frequency
Ranges: Added callouts for existing Footnote (3) to the
four CLKIN parameters. Added new Footnote (4) to the four CLKIN parameters. Added
new Footnote (5) to CLK2X, CLK2X180. Added new Footnote (6) to CLK2X,
CLK2X180; CLK0, CLK180; and CLKIN (using DLL outputs).
Recompiled for backward compatibility with Acrobat 4 and above. No content
changes.
Table
2,
Recommended Operating
limit from 1.8V to 1.6V.
Table
5,
Power-On Current for Virtex-II Pro
listed I
values apply to the entire device (all banks).
CCOMIN
Table
37,
Output Delay Measurement
1.4V to 1.65V.
Table
54,
Operating Frequency
Ranges: Corrected CLKOUT_FREQ_1X_LF_MAX and
CLKIN_FREQ_DLL_LF_MAX for -7 devices from 210 MHz to 270 MHz.
Table
62,
Package
Skew: Removed XC2VP40FF1517.
www.xilinx.com
Revision
, and I
.
CCAUXQ
(MGT receiver latency) max value.
RXLAT
Conditions: Revised Footnotes (4) and (6).
Characteristics: Added Footnote (1) referring
Characteristics.
through
page
39, and
JTAG Test
40, with improved timing diagrams,
Characteristics, and
Table
.
CC_STARTUP
Characteristics: Broke out T
SMDCC
Conditions: Corrected VTTX/VTRX lower voltage
Devices: Added Footnote (2) stating that
Methodology: Corrected V
MEAS
48,
SelectMAP
/T
,
SMCCD
for LVTTL from
Module 3 of 4
55