XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Date
Version
11/17/04
4.1
03/01/05
4.2
06/20/05
4.3
DS083 (v4.7) November 5, 2007
Product Specification
Figure
8,
Figure
9: Corrected T
CCO
Table
23: Added Footnote (4) to T
PHASE
Corrected T
from Typ to Max specification. Additional description of “2X
LOCK
oversampling” added to half-rate operation condition for F
(2) requiring use of oversampling techniques in XAPP572 for serial bit rates under
1 Gb/s.
Table
25: Converted bit rate conditions for jitter parameters into four ranges. Added
Footnote (2) requiring use of oversampling techniques in XAPP572 for serial bit rates
under 1 Gb/s.
Table
27: Additional description of “2X oversampling” added to half-speed clock
description for F
. Converted bit rate conditions for jitter parameters into four
GGTX
ranges. Added Footnotes (3) and (4) requiring use of oversampling techniques in
XAPP572 for serial bit rates under 1 Gb/s.
Table
37: Changed capacitance C
REF
Table
46: Added Min/Max specifications for T
Section
Power-On Power Supply Requirements, page
to description of V
ramp-on requirements. Removed requirement that V
CCINT
must be powered on before or with V
Updated values in
Virtex-II Pro Performance Characteristics
Switching Characteristics
tables, based on values extracted from speedsfile version
1.90.
Table 1
and
Table
2: Corrected VCCAUXTX and VCCAUXRX to AVCCAUXTX and
AVCCAUXRX respectively.
Table
3: Further clarified P
(MGT power dissipation) by explaining measurement
RXTX
method in Footnote (3).
Table
5: Added power-on current specifications for XC2VPX70 device.
Table
22: Changed F
from ±100 ppm to ±350 ppm.
GTOL
Table 22
and
Table
23: Changed T
GJTT
ranges.
Table
33,
Table
35,
Table
36, and
Table
include descriptions, as well as the actual IOSTANDARD attributes (used in the Xilinx
ICE™ software) for all I/O standards.
Table
33: Rearranged I/O standards in a more logical order.
Table
34: Added parameter T
(Minimum Pulse Width, SR Input).
RPW
Table
35: Changed “Csl” to “C
” to agree with
REF
I/O standards in a more logical order.
Table
36: Added footnote defining equivalents for DCI standards.
Table
37: Added Footnotes (2) and (3) to PCI/PCI-X capacitive load (C
Table
44: Added parameter T
, CLKA to CLKB Setup Time.
BCCS
Table
47: Added Footnote (1) indicating that F
F
if CCLK frequency is not adjustable.
CC_STARTUP
Table
49: T
corrected from a “Min” to a “Max” specification.
TCKTDO
Table
12: Added specifications for Differential Input Impedance.
www.xilinx.com
Revision
/ DOUT to refer to the falling edge of CCLK.
indicating an 8B/10B-type bitstream.
, and added Footnote
GCLK
for all PCI/PCI-X standards from 0 pF to 10 pF.
.
ICCK
5: Added word “monotonically”
.
CCO
and
Virtex-II Pro
bit rate qualifiers from fixed bit rates to bit rate
37: Restructured these I/O-related tables to
Figure 6
and
Table
37. Rearranged
REF
should not exceed
CC_SERIAL
CCAUX
) values.
Module 3 of 4
56