XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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Virtex-II Pro Pin Definitions
This section describes the pinouts for Virtex-II Pro devices
in the following packages:
FG256/FGG256, FG456/FGG456, and FG676/FGG676:
wire-bond fine-pitch BGA of 1.00 mm pitch
FF672, FF896, FF1148, FF1152, FF1517, FF1696,
and FF1704: flip-chip fine-pitch BGA of 1.00 mm pitch
All of the devices supported in a particular package are
pinout-compatible and are listed in the same table (one
Pin Definitions
Table 4
provides a description of each pin type listed in Virtex-II Pro pinout tables.
Table 4: Virtex-II Pro Pin Definitions
Pin Name
Direction
User I/O Pins:
IO_LXXY_#
Input/Output/
Bidirectional
Dual-Function Pins:
IO_LXXY_#/ZZZ
The dual-function pins are labelled “IO_LXXY_#/ ZZZ”, where "ZZZ" can be one of the following pins:
Per Bank - VRP, VRN, or VREF
Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, D0/DIN – D7, RDWR_B, or CS_B
These dual functions are defined in the following section:
"ZZZ" (Dual Function) Definitions:
Input/Output •
D0/DIN, D1, D2,
D3, D4, D5, D6,
D7
CS_B
Input
RDWR_B
Input
BUSY/DOUT
Output
INIT_B
Bidirectional
(open-drain)
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
table per package). Pins that are not available for smaller
devices are listed in right-hand columns.
Each device is split into eight I/O banks to allow for flexibility
in the choice of I/O standards. Global pins, including JTAG,
configuration, and power/ground pins, are listed at the end
of each table.
All Virtex-II Pro pinout tables are available on the distribu-
tion CD-ROM, or on the web (at
All user I/O pins are capable of differential signalling and can implement LVDS,
ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled “IO_LXXY_#”,
where:
IO indicates a user I/O pin.
LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for
the positive and negative sides of the differential pair.
# indicates the bank number (0 through 7)
In SelectMAP mode, D0 through D7 are configuration data pins. These pins
become user I/Os after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O
after configuration.
In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
In SelectMAP mode, BUSY controls the rate at which configuration data is loaded.
The pin becomes a user I/O after configuration, unless the SelectMAP port is
retained.
In bit-serial modes, DOUT provides preamble and configuration data to
downstream devices in a daisy-chain. The pin becomes a user I/O after
configuration.
When Low, this pin indicates that the configuration memory is being cleared. When
held Low, the start of configuration is delayed. During configuration, a Low on this
output indicates that a configuration data error has occurred. The pin becomes a user
I/O after configuration.
www.xilinx.com
Table 4
provides definitions for all pin types.
http://www.xilinx.com
Description
).
Module 4 of 4
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