XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 144

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
FG456/FGG456 Fine-Pitch BGA Package
As shown in
BGA package. The pins in these devices are same, except for the differences shown in the "No Connects" column. Following
this table are the
Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7
DS083 (v4.7) November 5, 2007
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
R
Table
FG456/FGG456 Fine-Pitch BGA Package Specifications (1.00mm
6, XC2VP2, XC2VP4, and XC2VP7 Virtex-II Pro devices are available in the FG456/FGG456 fine-pitch
IO_L74N_0/GCLK7P
IO_L74P_0/GCLK6S
IO_L75N_0/GCLK5P
IO_L75P_0/GCLK4S
IO_L75N_1/GCLK3P
IO_L75P_1/GCLK2S
IO_L74N_1/GCLK1P
IO_L74P_1/GCLK0S
IO_L69N_1/VREF_1
IO_L09N_1/VREF_1
IO_L03P_0/VREF_0
IO_L09P_0/VREF_0
IO_L69P_0/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L05_0/No_Pair
Pin Description
IO_L02N_0
IO_L02P_0
IO_L03N_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L09N_0
IO_L67N_0
IO_L67P_0
IO_L69N_0
IO_L69P_1
IO_L67N_1
IO_L67P_1
IO_L09P_1
IO_L07N_1
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
www.xilinx.com
Pin Number
D10
C10
D11
C11
C12
D12
C13
D13
D14
F10
E10
B11
F11
E11
E12
F12
B12
E13
F13
E14
D5
D6
E6
E7
D7
C7
E8
D8
C8
E9
D9
F9
XC2VP2
pitch).
No Connects
XC2VP4
Module 4 of 4
XC2VP7
16

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