XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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Single-cycle and multi-cycle mode option for I-side and
D-side interfaces
Single cycle = one CPU clock cycle;
multi-cycle = minimum of two and maximum of eight
CPU clock cycles
FPGA configurable DCR addresses within DSOCM
and ISOCM.
Independent 16 MB logical memory space available
within PPC405 memory map for each of the DSOCM
and ISOCM. The number of block RAMs in the device
might limit the maximum amount of OCM supported.
Maximum of 64K and 128K bytes addressable from
DSOCM and ISOCM interfaces, respectively, using
address outputs from OCM directly without additional
decoding logic.
Data-Side OCM (DSOCM)
32-bit Data Read bus and 32-bit Data Write bus
Byte write access to DSBRAM support
Second port of dual port DSBRAM is available to
read/write from an FPGA interface
22-bit address to DSBRAM port
8-bit DCR Registers: DSCNTL, DSARC
Three alternatives to write into DSBRAM: BRAM
initialization, CPU, FPGA H/W using second port
Instruction-Side OCM (ISOCM)
The ISOCM interface contains a 64-bit read only port, for
instruction fetches, and a 32-bit write only port, to initialize
or test the ISBRAM. When implementing the read only port,
the user must deassert the write port inputs. The preferred
method of initializing the ISBRAM is through the configura-
tion bitstream.
64-bit Data Read Only bus (two instructions per cycle)
32-bit Data Write Only bus (through DCR)
Separate 21-bit address to ISBRAM
8-bit DCR Registers: ISCNTL, ISARC
32-bit DCR Registers: ISINIT, ISFILL
Two alternatives to write into ISBRAM: BRAM
initialization, DCR and write instruction
Clock/Control Interface Logic
The clock/control interface logic provides proper initializa-
tion and connections for PPC405 clock/power manage-
ment, resets, PLB cycle control, and OCM interfaces. It also
couples user signals between the FPGA fabric and the
embedded PPC405 CPU core.
The processor clock connectivity is similar to CLB clock
pins. It can connect either to global clock nets or general
routing resources. Therefore the processor clock source
can come from DCM, CLB, or user package pin.
CPU-FPGA Interfaces
All Processor Block user pins link up with the general FPGA
routing resources through the CPU-FPGA interface. There-
fore processor signals have the same routability as other
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
non-Processor Block user signals. Longlines and hex lines
travel across the Processor Block both vertically and hori-
zontally, allowing signals to route through the Processor
Block.
Processor Local Bus (PLB) Interfaces
The PPC405 core accesses high-speed system resources
through PLB interfaces on the instruction and data cache
controllers. The PLB interfaces provide separate 32-bit
address/64-bit data buses for the instruction and data sides.
The cache controllers are both PLB masters. PLB arbiters
are implemented in the FPGA fabric and are available as
soft IP cores.
Device Control Register (DCR) Bus Interface
The device control register (DCR) bus has 10 bits of
address space for components external to the PPC405
core. Using the DCR bus to manage status and configura-
tion registers reduces PLB traffic and improves system
integrity. System resources on the DCR bus are protected
or isolated from wayward code since the DCR bus is not
part of the system memory map.
External Interrupt Controller (EIC) Interface
Two level-sensitive user interrupt pins (critical and non-criti-
cal) are available. They can be either driven by user defined
logic or Xilinx soft interrupt controller IP core outside the
Processor Block.
Clock/Power Management (CPM) Interface
The CPM interface supports several methods of clock distri-
bution and power management. Three modes of operation
that reduce power consumption below the normal opera-
tional level are available.
Reset Interface
There are three user reset input pins (core, chip, and sys-
tem) and three user reset output pins for different levels of
reset, if required.
Debug Interface
Debugging interfaces on the embedded PPC405 core, con-
sisting of the JTAG and Trace ports, offer access to
resources internal to the core and assist in software devel-
opment. The JTAG port provides basic JTAG chip testing
functionality as well as the ability for external debug tools to
gain control of the processor for debug purposes. The Trace
port furnishes programmers with a mechanism for acquiring
instruction execution traces.
The JTAG port is compatible with IEEE Std 1149.1, which
defines a test access port (TAP) and Boundary-Scan
architecture. Extensions to the JTAG interface provide
debuggers with processor control that includes stopping,
starting, and stepping the PPC405 core. These extensions
are compliant with the IEEE 1149.1 specifications for
vendor-specific extensions.
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