XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
The Trace port provides instruction execution trace informa-
tion to an external trace tool. The PPC405 core is capable of
back trace and forward trace. Back trace is the tracing of
instructions prior to a debug event while forward trace is the
tracing of instructions after a debug event.
The processor JTAG port and the FPGA JTAG port can be
accessed independently, or the two can be programmati-
cally linked together and accessed via the dedicated FPGA
JTAG pins.
For detailed information on the PPC405 JTAG interface,
please refer to the "JTAG Interface" section of the
405 Processor Block Reference Guide
CoreConnect™ Bus Architecture
The Processor Block is compatible with the CoreConnect™
bus architecture. Any CoreConnect compliant cores includ-
ing Xilinx soft IP can integrate with the Processor Block
through this high-performance bus architecture imple-
mented on FPGA fabric.
The CoreConnect architecture provides three buses for
interconnecting Processor Blocks, Xilinx soft IP, third party
IP, and custom logic, as shown in
Figure
Functional Description: Embedded PowerPC 405 Core
This section offers a brief overview of the various functional blocks shown in
PLB Master
Interface
I-Cache
I-Cache
Array
Controller
Instruction
Cache
Unit
Cache Units
Data
Cache
Unit
D-Cache
D-Cache
Array
Controller
PLB Master
Interface
Figure 16: Embedded PPC405 Core Block Diagram
Embedded PPC405 Core
The embedded PPC405 core is a 32-bit Harvard architec-
ture processor.
Figure 16
illustrates its functional blocks:
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
System
PowerPC
Processor Local Bus (PLB)
On-Chip Peripheral Bus (OPB)
Device Control Register (DCR) bus
High-performance peripherals connect to the high-band-
width, low-latency PLB. Slower peripheral cores connect to
the OPB, which reduces traffic on the PLB, resulting in
greater overall system performance.
For more information, refer to:
http://www-3.ibm.com/chips/techlib/techlib.nfs/productfa
15:
milies/CoreConnect_Bus_Architecture/
Instruction
OCM
MMU
Fetch & Decode
Fetch
Instruction Shadow
and
TLB
Decode
(4 Entry)
Logic
Unified TLB
(64 Entry)
Data Shadow
Execution Unit (EXU)
TLB
(8 Entry)
32 x 32
GPR
Execution Unit
Data
OCM
Cache units
Memory Management unit
Fetch Decode unit
www.xilinx.com
DCR
System
System
Peripheral
Bus
Core
Core
Core
Core
Bus
Processor Local Bus
On-Chip Peripheral Bus
Bridge
CoreConnect Bus Architecture
Instruction
Data
Processor
Block
DCR Bus
Figure 15: CoreConnect Block Diagram
Figure
16.
Timers
3-Element
(FIT,
Fetch
PIT,
Queue
Watchdog)
(PFB1,
PFB0,
DCD)
Timers
&
Debug
Debug Logic
ALU
MAC
JTAG
Instruction
Trace
DS083-2_01_062001
Peripheral
Core
DS083-2_02a_010202
Module 2 of 4
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