XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Execution unit
Timers
Debug logic unit
It operates on instructions in a five stage pipeline consisting
of a fetch, decode, execute, write-back, and load write-back
stage. Most instructions execute in a single cycle, including
loads and stores.
Instruction and Data Cache
The embedded PPC405 core provides an instruction cache
unit (ICU) and a data cache unit (DCU) that allow concur-
rent accesses and minimize pipeline stalls. The instruction
and data cache array are 16 KB each. Both cache units are
two-way set associative. Each way is organized into 256
lines of 32 bytes (eight words). The instruction set provides
a rich assortment of cache control instructions, including
instructions to read tag information and data arrays.
The PPC405 core accesses external memory through the
instruction (ICU) and data cache units (DCU). The cache
units each include a 64-bit PLB master interface, cache
arrays, and a cache controller. The ICU and DCU handle
cache misses as requests over the PLB to another PLB
device such as an external bus interface unit. Cache hits are
handled as single cycle memory accesses to the instruction
and data caches.
Instruction Cache Unit (ICU)
The ICU provides one or two instructions per cycle to the
instruction queue over a 64-bit bus. A line buffer (built into
the output of the array for manufacturing test) enables the
ICU to be accessed only once for every four instructions, to
reduce power consumption by the array.
The ICU can forward any or all of the four or eight words of
a line fill to the EXU to minimize pipeline stalls caused by
cache misses. The ICU aborts speculative fetches aban-
doned by the EXU, eliminating unnecessary line fills and
enabling the ICU to handle the next EXU fetch. Aborting
abandoned requests also eliminates unnecessary external
bus activity, thereby increasing external bus utilization.
Data Cache Unit (DCU)
The DCU transfers one, two, three, four, or eight bytes per
cycle, depending on the number of byte enables presented
by the CPU. The DCU contains a single-element command
and store data queue to reduce pipeline stalls; this queue
enables the DCU to independently process load/store and
cache control instructions. Dynamic PLB request prioritiza-
tion reduces pipeline stalls even further. When the DCU is
busy with a low-priority request while a subsequent storage
operation requested by the CPU is stalled; the DCU auto-
matically increases the priority of the current request to the
PLB.
The DCU provides additional features that allow the pro-
grammer to tailor its performance for a given application.
The DCU can function in write-back or write-through mode,
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
as controlled by the Data Cache Write-through Register
(DCWR) or the Translation Look-aside Buffer (TLB); the
cache controller can be tuned for a balance of performance
and memory coherency. Write-on-allocate, controlled by the
store word on allocate (SWOA) field of the Core Configura-
tion Register 0 (CCR0), can inhibit line fills caused by store
misses, to further reduce potential pipeline stalls and
unwanted external bus traffic.
Fetch and Decode Logic
The fetch/decode logic maintains a steady flow of instruc-
tions to the execution unit by placing up to two instructions
in the fetch queue. The fetch queue consists of three buff-
ers: pre-fetch buffer 1 (PFB1), pre-fetch buffer 0 (PFB0),
and decode (DCD). The fetch logic ensures that instructions
proceed directly to decode when the queue is empty.
Static branch prediction as implemented on the PPC405
core takes advantage of some standard statistical proper-
ties of code. Branches with negative address displacement
are by default assumed taken. Branches that do not test the
condition or count registers are also predicted as taken. The
PPC405 core bases branch prediction upon these default
conditions when a branch is not resolved and speculatively
fetches along the predicted path. The default prediction can
be overridden by software at assembly or compile time.
Branches are examined in the decode and pre-fetch buffer 0
fetch queue stages. Two branch instructions can be handled
simultaneously. If the branch in decode is not taken, the
fetch logic fetches along the predicted path of the branch
instruction in pre-fetch buffer 0. If the branch in decode is
taken, the fetch logic ignores the branch instruction in
pre-fetch buffer 0.
Execution Unit
The embedded PPC405 core has a single issue execution
unit (EXU) containing the register file, arithmetic logic unit
(ALU), and the multiply-accumulate (MAC) unit. The execu-
tion unit performs all 32-bit PowerPC integer instructions in
hardware.
The register file is comprised of thirty-two 32-bit general
purpose registers (GPR), which are accessed with three
read ports and two write ports. During the decode stage,
data is read out of the GPRs and fed to the execution unit.
Likewise, during the write-back stage, results are written to
the GPR. The use of the five ports on the register file
enables either a load or a store operation to execute in par-
allel with an ALU operation.
Memory Management Unit (MMU)
The embedded PPC405 core has a 4 GB address space,
which is presented as a flat address space.
The MMU provides address translation, protection func-
tions, and storage attribute control for embedded applica-
tions. The MMU supports demand-paged virtual memory
and other management schemes that require precise con-
trol of logical-to-physical address mapping and flexible
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