XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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Functional Description: FPGA
Input/Output Blocks (IOBs)
Virtex-II Pro I/O blocks (IOBs) are provided in groups of two
or four on the perimeter of each device. Each IOB can be
used as input and/or output for single-ended I/Os. Two IOBs
can be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in
Figure
18.
IOB blocks are designed for high-performance I/O, support-
ing 22 single-ended standards, as well as differential sig-
naling with LVDS, LDT, bus LVDS, and LVPECL.
IOB
PAD4
IOB
PAD3
Switch
Matrix
IOB
PAD2
IOB
PAD1
Figure 18: Virtex-II Pro Input/Output Tile
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II Pro IOB blocks feature SelectIO-Ultra inputs and
outputs that support a wide variety of I/O signaling stan-
dards.
In
addition
to
the
internal
(V
= 1.5V), output driver supply voltage (V
CCINT
dependent on the I/O standard (see
An auxiliary supply voltage (V
CCAUX
regardless of the I/O standard used. For exact supply volt-
age absolute maximum ratings, see
Virtex-II Pro X Platform FPGAs: DC and Switching Charac-
teristics.
All of the user IOBs have fixed-clamp diodes to V
ground. The IOBs are not compatible or compliant with 5V
I/O standards (not 5V-tolerant).
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Table 10
lists supported I/O standards with Digitally Con-
trolled Impedance. See
(DCI), page
Table 8: Supported Single-Ended I/O Standards
IOSTANDARD
Attribute
(1)
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
Differential Pair
PCI33_3
PCI66_3
PCIX
GTL
Differential Pair
GTLP
HSTL_I
DS083-2_30_010202
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
supply
voltage
HSTL_III _18
) is
CCO
Table 8
and
Table
9).
HSTL_IV_18
= 2.5V) is required,
SSTL2_I
SSTL2_II
Virtex-II Pro and
SSTL18_I
SSTL18_II
and to
CCO
Notes:
1.
Refer to
standards.
2.
For PCI and PCI-X standards, refer to XAPP653.
3.
V
of GTL or GTLP should not be lower than the termination
CCO
voltage or the voltage seen at the I/O pad. Example: If the pin High
level is 1.5V, connect V
4.
SSTL18_I is not a JEDEC-supported standard.
5.
N/R = no requirement.
www.xilinx.com
Digitally Controlled Impedance
31.
Output
Input
Input
V
V
V
Voltage (V
CCO
CCO
REF
3.3
3.3
N/R
(1)
3.3
3.3
N/R
2.5
2.5
N/R
1.8
1.8
N/R
1.5
1.5
N/R
Note (2)
Note (2)
N/R
Note (2)
Note (2)
N/R
Note (2)
Note (2)
N/R
Note (3)
Note (3)
0.8
Note (3)
Note (3)
1.0
1.5
N/R
0.75
1.5
N/R
0.75
1.5
N/R
0.9
1.5
N/R
0.9
1.8
N/R
0.9
1.8
N/R
0.9
1.8
N/R
1.1
1.8
N/R
1.1
2.5
N/R
1.25
2.5
N/R
1.25
(4)
1.8
N/R
0.9
1.8
N/R
0.9
XAPP659
for more details on interfacing to these 3.3V
to 1.5V.
CCO
Board
Termination
)
TT
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.2
1.5
0.75
0.75
1.5
1.5
0.9
0.9
1.8
1.8
1.25
1.25
0.9
0.9
Module 2 of 4
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