XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Table 9: Supported Differential Signal I/O Standards
Output
Input
I/O Standard
V
V
CCO
CCO
LDT_25
2.5
N/R
LVDS_25
2.5
N/R
LVDSEXT_25
2.5
N/R
BLVDS_25
2.5
N/R
ULVDS_25
2.5
N/R
LVPECL_25
2.5
N/R
(1)
LDT_25_DT
2.5
2.5
(1)
LVDS_25_DT
2.5
2.5
(1)
LVDSEXT_25_DT
2.5
2.5
(1)
ULVDS_25_DT
2.5
2.5
Notes:
1.
These standards support on-chip 100Ω termination.
2.
N/R = no requirement.
Table 10: Supported DCI I/O Standards
Output
Input
I/O Standard
V
V
CCO
CCO
(1)
LVDCI_33
3.3
3.3
LVDCI_25
2.5
2.5
LVDCI_DV2_25
2.5
2.5
LVDCI_18
1.8
1.8
LVDCI_DV2_18
1.8
1.8
LVDCI_15
1.5
1.5
LVDCI_DV2_15
1.5
1.5
GTL_DCI
1.2
1.2
GTLP_DCI
1.5
1.5
HSTL_I_DCI
1.5
1.5
HSTL_II_DCI
1.5
1.5
HSTL_III_DCI
1.5
1.5
HSTL_IV_DCI
1.5
1.5
HSTL_I_DCI_18
1.8
1.8
HSTL_II_DCI_18
1.8
1.8
HSTL_III_DCI_18
1.8
1.8
HSTL_IV_DCI_18
1.8
1.8
(2)
SSTL2_I_DCI
2.5
2.5
(2)
SSTL2_II_DCI
2.5
2.5
(3)
SSTL18_I_DCI
1.8
1.8
SSTL18_II_DCI
1.8
1.8
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Table 10: Supported DCI I/O Standards (Continued)
Input
Output
I/O Standard
V
V
REF
OD
LVDS_25_DCI
N/R
0.500 – 0.740
LVDSEXT_25_DCI
N/R
0.247 – 0.454
Notes:
N/R
0.440 – 0.820
1.
LVDCI_XX is LVCMOS output controlled impedance buffers,
matching all or half of the reference resistors.
N/R
0.250 – 0.450
2.
These are SSTL compatible.
N/R
0.500 – 0.740
3.
SSTL18_I is not a JEDEC-supported standard.
4.
N/R = no requirement.
N/R
0.345 – 1.185
Logic Resources
N/R
0.500 – 0.740
N/R
0.247 – 0.454
IOB blocks include six storage elements, as shown in
Figure
19.
N/R
0.330 – 0.700
N/R
0.500 – 0.740
Reg
OCK1
Termination
Input
V
Type
REF
Reg
N/R
Series
OCK2
N/R
Series
N/R
Series
N/R
Series
Reg
N/R
Series
OCK1
N/R
Series
N/R
Series
Reg
0.8
Single
OCK2
1.0
Single
0.75
Split
0.75
Split
0.9
Single
0.9
Single
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
0.9
Split
On the input, output, and 3-state path, one or two DDR reg-
0.9
Split
isters can be used.
1.1
Single
Double data rate is directly accomplished by the two regis-
1.1
Single
ters on each path, clocked by the rising edges (or falling
1.25
Split
edges) from two different clock nets. The two clock signals
1.25
Split
are generated by the DCM and must be 180 degrees out of
0.9
Split
phase, as shown in
0.9
Split
and 3-state data signals, each being alternately clocked out.
www.xilinx.com
Termination
Output
Input
Input
V
V
V
CCO
CCO
REF
2.5
2.5
N/R
2.5
2.5
N/R
IOB
Input
DDR mux
Reg
ICK1
3-State
Reg
ICK2
DDR mux
PAD
Output
DS031_29_100900
Figure 19: Virtex-II Pro IOB Block
Figure
20. There are two input, output,
Type
Split
Split
Module 2 of 4
25