XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 40

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
R
Bank 0
Bank 1
Bank 5
Bank 4
Figure 24: I/O Banks: Wire-Bond Packages (FG)
Top View
Bank 1
Bank 0
Bank 4
Bank 5
Figure 25: I/O Banks: Flip-Chip Packages (FF)
Top View
Some input standards require a user-supplied threshold
voltage (V
), and certain user-I/O pins are automatically
REF
configured as V
inputs. Approximately one in six of the
REF
I/O pins in the bank assume this role.
V
pins within a bank are interconnected internally, thus
REF
only one V
voltage can be used within each bank. How-
REF
ever, for correct operation, all V
REF
connected to the external reference voltage source.
The V
and the V
pins for each bank appear in the
CCO
REF
device pinout tables. Within a given package, the number of
V
and V
pins can vary depending on the size of
REF
CCO
device. In larger devices, more I/O pins convert to V
pins. Since these are always a superset of the V
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All V
pins for the largest device anticipated must be con-
REF
nected to the V
voltage and not used for I/O. In smaller
REF
devices, some V
pins used in larger devices do not con-
CCO
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
nect within the package. These unconnected pins can be
left unconnected externally, or, if necessary, they can be
connected to V
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different
input, output, and bi-directional standards in the same bank:
1. Combining output standards only. Output standards
with the same output V
combined in the same bank.
Compatible example:
Incompatible example:
ug002_c2_014_041403
2. Combining input standards only. Input standards
with the same input V
can be combined in the same bank.
Compatible example:
Incompatible example:
Incompatible example:
3. Combining input standards and output standards.
Input standards and output standards with the same
input V
combined in the same bank.
Compatible example:
ds031_66_041403
Incompatible example:
4. Combining bi-directional standards with input or
output standards. When combining bi-directional I/O
with other standards, make sure the bi-directional
standard can meet rules 1 through 3 above.
5. Additional rules for combining DCI I/O standards.
a. No more than one Single Termination type (input or
pins in the bank must be
b. No more than one Split Termination type (input or
REF
pins
REF
The implementation tools will enforce the above design
rules.
Table 12, page
supplies.
www.xilinx.com
to permit migration to a larger device.
CCO
requirement can be
CCO
SSTL2_I and LVDS_25 outputs
SSTL2_I (output V
= 2.5V) and
CCO
LVCMOS33 (output V
= 3.3V) outputs
CCO
and input V
CCO
REF
LVCMOS15 and HSTL_IV inputs
LVCMOS15 (input V
= 1.5V) and
CCO
LVCMOS18 (input V
= 1.8V) inputs
CCO
HSTL_I_DCI_18 (V
= 0.9V) and
REF
HSTL_IV_DCI_18 (V
= 1.1V) inputs
REF
and output V
requirement can be
CCO
CCO
LVDS_25 output and HSTL_I input
LVDS_25 output (output V
= 2.5V) and
CCO
HSTL_I_DCI_18 input (input V
= 1.8V)
CCO
output) is allowed in the same bank.
Incompatible example:
HSTL_IV_DCI input and HSTL_III_DCI input
output) is allowed in the same bank.
Incompatible example:
HSTL_I_DCI input and HSTL_II_DCI input
30, summarizes all standards and voltage
requirements
Module 2 of 4
29

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