XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 48

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
R
DY
D
CE
CK
SR REV
BY
DX
D
CE
CE
CK
CLK
SR REV
SR
BX
Figure 35: Register / Latch Configuration in a Slice
The set and reset functionality of a register or a latch can be
configured as follows:
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
The synchronous reset has precedence over a set, and an
asynchronous clear has precedence over a preset.
Distributed SelectRAM+ Memory
Each function generator (LUT) can implement a 16 x 1-bit
synchronous
RAM
resource
SelectRAM+ element. SelectRAM+ elements are config-
urable within a CLB to implement the following:
Single-Port 16 x 8-bit RAM
Single-Port 32 x 4-bit RAM
Single-Port 64 x 2-bit RAM
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Single-Port 128 x 1-bit RAM
Dual-Port 16 x 4-bit RAM
FFY
Dual-Port 32 x 2-bit RAM
FF
LATCH
Dual-Port 64 x 1-bit RAM
Distributed SelectRAM+ memory modules are synchronous
YQ
Q
(write) resources. The combinatorial read access time is
Attribute
extremely fast, while the synchronous write simplifies
INIT1
high-speed designs. A synchronous read can be imple-
INIT0
mented with a storage element in the same slice. The dis-
SRHIGH
tributed SelectRAM+ memory and the storage element
SRLOW
share the same clock input. A Write Enable (WE) input is
FFX
active High, and is driven by the SR input.
FF
LATCH
Table 16
by each distributed SelectRAM+ configuration.
XQ
Q
Attribute
Table 16: Distributed SelectRAM+ Configurations
INIT1
INIT0
SRHIGH
SRLOW
Reset Type
SYNC
ASYNC
DS083-2_22_122001
Notes:
1. S = single-port configuration; D = dual-port configuration
For single-port configurations, distributed SelectRAM+
memory has one address port for synchronous writes and
asynchronous reads.
For dual-port configurations, distributed SelectRAM+ mem-
ory has one port for synchronous writes and asynchronous
reads and another port for asynchronous reads. The func-
tion generator (LUT) has separated read address inputs
(A1, A2, A3, A4) and write address inputs (WG1/WF1,
WG2/WF2, WG3/WF3, WG4/WF4).
called
a
distributed
In single-port mode, read and write addresses share the
same address bus. In dual-port mode, one function genera-
tor (R/W port) is connected with shared read and write
addresses. The second function generator has the A inputs
(read) connected to the second read-only port address and
the W inputs (write) shared with the first read/write port
www.xilinx.com
shows the number of LUTs (2 per slice) occupied
RAM
Number of LUTs
16 x 1S
1
16 x 1D
2
32 x 1S
2
32 x 1D
4
64 x 1S
4
64 x 1D
8
128 x 1S
8
Module 2 of 4
37

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