XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Each RocketIO or RocketIO X core implements the following
technology:
Serializer and deserializer (SERDES)
Monolithic clock synthesis and clock recovery (CDR)
10 Gigabit Attachment Unit Interface (XAUI) Fibre
Channel (3.1875 Gb/s XAUI), Infiniband, PCI Express,
Aurora, SXI-5 (SFI-5,/SPI-5), and OC-48
(1)
compatibility
8/16/32-bit (RocketIO) or 8/16/32/64-bit (RocketIO X)
selectable FPGA interface
8B/10B (RocketIO) or 8B/10B and 64B/66B
(RocketIO X) encoder and decoder with bypassing
option on each channel
Channel bonding support (two to twenty channels)
-
Elastic buffers for inter-chip deskewing and
channel-to-channel alignment
Receiver clock recovery tolerance of up to
75 non-transitioning bits
50Ω (RocketIO X) or 50Ω /75Ω selectable (RocketIO)
on-chip transmit and receive terminations
Programmable comma detection and word alignment
Rate matching via insertion/deletion characters
Automatic lock-to-reference function
Programmable pre-emphasis support
Per-channel serial and parallel transmitter-to-receiver
internal loopback modes
Optional transmit and receive data inversion
Cyclic Redundancy Check support (RocketIO only)
PowerPC 405 Processor Block
The PPC405 RISC CPU can execute instructions at a sus-
tained rate of one instruction per cycle. On-chip instruction
and data cache reduce design complexity and improve sys-
tem throughput.
The PPC405 features include:
PowerPC RISC CPU
-
Implements the PowerPC User Instruction Set
Architecture (UISA) and extensions for embedded
applications
-
Thirty-two 32-bit general purpose registers (GPRs)
-
Static branch prediction
-
Five-stage pipeline with single-cycle execution of
most instructions, including loads/stores
-
Unaligned and aligned load/store support to cache,
main memory, and on-chip memory
-
Hardware multiply/divide for faster integer
arithmetic (4-cycle multiply, 35-cycle divide)
-
Enhanced string and multiple-word handling
-
Big/little endian operation support
Storage Control
1. Refer to
Table 4, Module 2
for detailed information about RocketIO and RocketIO X transceiver compatible protocols.
2. Refer to
XAPP659
for more information.
3. Refer to
XAPP653
for more information.
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
-
Separate instruction and data cache units, both
two-way set-associative and non-blocking
-
Eight words (32 bytes) per cache line
-
16 KB array Instruction Cache Unit (ICU), 16 KB
array Data Cache Unit (DCU)
-
Operand forwarding during instruction cache line fill
-
Copy-back or write-through DCU strategy
-
Doubleword instruction fetch from cache improves
branch latency
Virtual mode memory management unit (MMU)
-
Translation of the 4 GB logical address space into
physical addresses
-
Software control of page replacement strategy
-
Supports multiple simultaneous page sizes ranging
from 1 KB to 16 MB
OCM controllers provide dedicated interfaces between
Block SelectRAM+ memory and processor block
instruction and data paths for high-speed access
PowerPC timer facilities
-
64-bit time base
-
Programmable interval timer (PIT)
-
Fixed interval timer (FIT)
-
Watchdog timer (WDT)
Debug Support
-
Internal debug mode
-
External debug mode
-
Debug Wait mode
-
Real Time Trace debug mode
-
Enhanced debug support with logical operators
-
Instruction trace and trace-back support
-
Forward or backward trace
Two hardware interrupt levels support
Advanced power management support
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
Input block with an optional single data rate (SDR) or
double data rate (DDR) register
Output block with an optional SDR or DDR register and
an optional 3-state buffer to be driven directly or
through an SDR or DDR register
Bidirectional block (any combination of input and output
configurations)
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
LVTTL, LVCMOS (3.3V,
PCI-X compatible (133 MHz and 66 MHz) at 3.3V
PCI compliant (66 MHz and 33 MHz) at 3.3V
GTL and GTLP
www.xilinx.com
(2)
2.5V, 1.8V, and 1.5V)
(3)
(3)
Module 1 of 4
4