XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
Page 55/430

Download datasheet (4Mb)Embed
PrevNext
R
CLB/Slice Configurations
Table 19
summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be
implemented in one of the configurations listed.
Table 19: Logic Resources in One CLB
Slices
LUTs
Flip-Flops
4
8
8
Table 20: Virtex-II Pro Logic Resources Available in All CLBs
CLB Array:
Number
Row x
Device
Column
Slices
XC2VP2
16 x 22
1,408
XC2VP4
40 x 22
3,008
XC2VP7
40 x 34
4,928
XC2VP20
56 x 46
9,280
XC2VPX20
56 x 46
9,792
XC2VP30
80 x 46
13,696
XC2VP40
88 x 58
19,392
XC2VP50
88 x 70
23,616
XC2VP70
104 x 82
33,088
XC2VPX70
104 x 82
33,088
XC2VP100
120 x 94
44,096
Notes:
1. The carry-chains and SOP chains can be split or cascaded.
18 Kb Block SelectRAM+ Resources
Introduction
Virtex-II Pro devices incorporate large amounts of 18 Kb
block SelectRAM+ resources. These complement the dis-
tributed SelectRAM+ resources that provide shallow RAM
structures implemented in CLBs. Each Virtex-II Pro block
SelectRAM+ resource is an 18 Kb true dual-port RAM with
two independently clocked and independently controlled
synchronous ports that access a common storage area.
Both ports are functionally identical. CLK, EN, WE, and
SSR polarities are defined through configuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM+ behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Table 20
shows the available resources in all CLBs.
Arithmetic &
MULT_ANDs
Carry-Chains
8
2
Number
Max Distributed
of
of
SelectRAM or Shift
LUTs
Register (bits)
2,816
45,056
6,016
96,256
9,856
157,696
18,560
296,960
19,584
313,334
27,392
438,272
38,784
620,544
47,232
755,712
66,176
1,058,816
66,176
1,058,816
88,192
1,411,072
Configuration
Virtex-II Pro block SelectRAM+ supports various configura-
tions, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in
Table 21: Dual- and Single-Port Configurations
Single-Port Configuration
As a single-port RAM, the block SelectRAM+ has access to
the 18 Kb memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kb
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
www.xilinx.com
SOP
Distributed
Shift
Chains
SelectRAM+
Registers
2
128 bits
128 bits
Number
Number
of
of
(1)
Flip-Flops
Carry-Chains
2,816
44
6,016
44
9,856
68
18,560
92
18,560
92
27,392
92
38,784
116
47,232
140
66,176
164
66,176
164
88,192
188
16K x 1 bit
2K x 9 bits
8K x 2 bits
1K x 18 bits
4K x 4 bits
512 x 36 bits
TBUF
2
Number
of SOP
(1)
Chains
32
80
80
112
112
160
176
176
208
208
240
Table
21.
Module 2 of 4
44