XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 60

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
R
8 clock pads
Virtex-II Pro
Device
8 clock pads
Figure 55: Virtex-II Pro Clock Pads
Figure 56: Virtex-II Pro Clock Multiplexer Buffer Configuration
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Each global clock multiplexer buffer can be driven either by
the clock pad to distribute a clock directly to the device, or
by the Digital Clock Manager (DCM), discussed in
Clock Manager (DCM), page
plexer buffer can also be driven by local interconnects. The
DCM has clock output(s) that can be connected to global
clock multiplexer buffer inputs, as shown in
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM+ blocks.
Eight global clocks can be used in each quadrant of the
Virtex-II Pro device. Designers should consider the clock
distribution detail of the device prior to pin-locking and floor-
planning. (See the Virtex-II Pro Platform FPGA User
DS083-2_42_052902
Guide.)
Clock
Pad
CLKIN
Clock
Pad
DCM
CLKOUT
Clock Multiplexer
I
Clock
Buffer
O
Clock Distribution
www.xilinx.com
51. Each global clock multi-
Figure
Local
Interconnect
DS083-2_43_122001
Digital
56.
Module 2 of 4
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