XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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Page 70/430

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Date
Version
03/24/03
2.5.1
05/27/03
2.6
06/02/03
2.7
08/25/03
2.7.1
09/10/03
2.8
10/14/03
2.9
12/10/03
3.0
02/19/04
3.1
03/09/04
3.1.1
04/22/04
3.2
06/30/04
4.0
Merged in DS110-2 (Module 2 of Virtex-II Pro X data sheet). Separate RocketIO and
RocketIO X sections created.
11/17/04
4.1
03/01/05
4.2
06/20/05
4.3
No changes in Module 2 for this revision.
09/15/05
4.4
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Table
10: Corrected I/O standard names SSTL18_I and SSTL18_II to SSTL18_I_DCI
and SSTL18_II_DCI respectively.
Figure
61, text below: Corrected wording of criteria for clock switching.
Removed Compatible Output Standards and Compatible Input Standards tables.
Added new
Table
12,
Summary of Voltage Supply Requirements for All Input and
Output
Standards. This table replaces deleted I/O standards tables.
Corrected sentence in section
Input/Output Individual Options, page
optional weak-keeper circuit is connected to each user I/O pad.”
Added section
Rules for Combining I/O Standards in the Same Bank, page
Added four Differential Termination I/O standards to
Added section
On-Chip Differential Termination
Added footnote referring to XAPP659 to 3.3V I/O callouts in
Section
Configuration, page
56: Added text indicating that the mode pins M0-M2 must
be held to a constant DC level during and after configuration.
Deleted section
Functional Description: RocketIO Multi-Gigabit Transceiver (MGT),
page
10. Added section
Local Clocking, page
Sections
Slave-Serial Mode
and
Master-Serial Mode, page
"falling" edge with respect to DOUT.
Table 8, page 24
and
Table 10, page
from 1.08V to 1.1V.
XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades
-5 and -6, are released to Production status.
Section
BUFGMUX, page
50: Corrected the definition of the "presently selected clock"
to be I0 or I1. Corrected signal names in
CLK1 to I0 and I1.
Recompiled for backward compatibility with Acrobat 4 and above. No content
changes.
Section
Clock De-skew, page
52: Removed reference to CLK2X as an option for DCM
clock feedback.
Figure 11, page
12: Corrected figure by removing coupling capacitors from input.
Section
Rules for Combining I/O Standards in the Same Bank, page
standard in the first example from LVDS_25_DCI to LVDS_25.
Reassigned heading hierarchies for better agreement with content.
Table
7: Corrected VCCAUXTX and VCCAUXRX to AVCCAUXTX and AVCCAUXRX
respectively.
Table
9: Corrected V
(output voltage) range for LVDSEXT_25.
OD
Table
25: Corrected SelectRAM+ memory available for XC2VPX70 device.
Table
33: Updated configuration default bitstream lengths.
Table
1: Deleted SONET OC-192 protocol.
Table
3: Deleted RocketIO X primitives for SONET OC-192, 10 Gbit Ethernet, and
Xilinx 10G (Aurora) protocols.
Changed all instances of 10.3125 Gb/s to 6.25 Gb/s.
Table
7: Changed RocketIO X VCCAUXRX from 1.5V globally to 1.5V for 8B/10B
encoding, 1.8V for all other encoding protocols.
www.xilinx.com
Revision
27, to read “The
Table 9
and
Table
12.
and
Figure 31, page
34.
Table 8
and
51.
56: Changed "rising" to
25: Corrected Input V
for HSTL_III-IV_18
REF
Figure 61
and associated text from CLK0 and
29: Corrected I/O
29.
Table
12.
Module 2 of 4
59