XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
RocketIO Switching Characteristics
Table 22: RocketIO X Reference Clock Switching Characteristics
Description
(1)
Reference Clock frequency range
Reference Clock frequency tolerance
Reference Clock rise time
Reference Clock fall time
Reference Clock duty cycle
Reference Clock total jitter, peak-peak
Clock recovery frequency acquisition time,
from Power-up to High state of PMARXLOCK
Clock recovery phase acquisition time,
from Data to High state of PMARXLOCK
Notes:
1.
BREFCLK should be used for all serial bit rates up to the maximum shown.
Table 23: RocketIO Reference Clock Switching Characteristics
Description
(1)
Reference Clock frequency range
Reference Clock frequency tolerance
Reference Clock rise time
Reference Clock fall time
Reference Clock duty cycle
Reference Clock total jitter, peak-peak
Clock recovery frequency acquisition time
Clock recovery phase acquisition time
Notes:
1.
BREFCLK/BREFCLK2 can be used for all serial bit rates up to the maximum shown. REFCLK/REFCLK2 can be used for serial bit rates up to
2.5 Gb/s (REFCLK = 125 MHz). All other parameters apply equally to REFCLK, REFCLK2, BREFCLK, and BREFCLK2 except as noted.
2.
For serial rates under 1 Gb/s, the 3X (or greater) oversampling techniques described in
receive jitter tolerance specifications defined in this data sheet.
3.
Measured at the package pin. For reference clock frequencies equal to or above 125 MHz, BREFCLK/BREFCLK2 must be used.
4.
8B/10B-type bitstream.
80%
20%
T
FCLK
DS083 (v4.7) November 5, 2007
Product Specification
Symbol
Conditions
F
GCLK
F
GTOL
T
20% – 80%
RCLK
T
20% – 80%
FCLK
T
DCREF
3.125 Gb/s – 6.25 Gb/s
T
GJTT
2.488 Gb/s – 3.125 Gb/s
T
LOCK
T
PHASE
Symbol
Conditions
Full rate operation
F
Half rate operation
GCLK
(2X oversampling)
F
GTOL
T
20% – 80%
RCLK
T
20% – 80%
FCLK
T
DCREF
2.501 Gb/s – 3.125 Gb/s
(3)
T
1.061 Gb/s – 2.5 Gb/s
GJTT
< 1.06 Gb/s
T
LOCK
T
PHASE
T
RCLK
Figure 3: Reference Clock Timing Parameters
www.xilinx.com
All Speed Grades
Min
Typ
Max
62.5
425
±350
75
75
45
50
55
30
40
100
40
60
All Speed Grades
Min
Typ
Max
50
156.25
(2)
60
100
±100
600
1000
600
1000
45
50
55
40
50
120
10
960
XAPP572
are required to meet the transmit jitter and
DS083-3_01_120302
Units
MHz
ppm
ps
ps
%
ps
ps
µs
µs
Units
MHz
MHz
ppm
ps
ps
%
ps
ps
ps
µs
(4)
bits
Module 3 of 4
14