XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 89

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 27: RocketIO Transmitter Switching Characteristics
Description
Serial data rate, full-speed clock
(3)
Serial data rate, half-speed clock
(2X oversampling)
Serial data output deterministic jitter
Serial data output random jitter
TX rise time
TX fall time
(5)
Transmit latency
TXUSRCLK duty cycle
TXUSRCLK2 duty cycle
Notes:
1.
Serial data rate in the -5 speed grade is limited to 2.0 Gb/s in both wirebond and flipchip packages.
2.
UI = Unit Interval
3.
For serial rates under 1 Gb/s, the 3X (or greater) oversampling techniques described in
receive jitter tolerance specifications defined in this data sheet.
4.
The oversampling techniques described in
5.
Transmit latency delay TXDATA to TXP/TXN. Refer to
. . . . .
1
2
TXP/TXN
DATA ORIGINATES
TXDATA[16:0]
0
TXUSRCLK2
Figure 5: RocketIO Transmit Latency (Maximum, Including CRC)
DS083 (v4.7) November 5, 2007
Product Specification
Symbol
Conditions
Flipchip packages
Wirebond packages
F
GTX
Flipchip packages
Wirebond packages
2.126 Gb/s – 3.125 Gb/s
1.0626 Gb/s – 2.125 Gb/s
T
DJ
1.0 Gb/s – 1.0625 Gb/s
600 Mb/s – 999 Mb/s
2.126 Gb/s – 3.125 Gb/s
1.0626 Gb/s – 2.125 Gb/s
T
RJ
1.0 Gb/s – 1.0625 Gb/s
600 Mb/s – 999 Mb/s
T
RTX
20% – 80%
T
FTX
Including CRC
T
TXLAT
Excluding CRC
T
TXDC
T
TX2DC
XAPP572
are required to meet these specifications for serial rates less than 1 Gb/s.
RocketIO Transceiver User Guide
. . . . .
20
21 22
320
321 322
T
TXLAT
1
16
www.xilinx.com
Min
Typ
Max
(1)
1.0
3.125
(1)
1.0
2.5
0.600
1.0
0.600
1.0
0.17
0.08
0.05
0.08
0.18
0.19
0.18
0.18
120
120
14
17
8
11
45
50
55
45
50
55
XAPP572
are required to meet the transmit jitter and
for more information on calculating latency.
. . . . .
. . . .
340 341 342
DATA ARRIVES
17
DS083-3_03_082301
Units
Gb/s
Gb/s
Gb/s
Gb/s
(2)
UI
UI
UI
(4)
UI
UI
UI
UI
(4)
UI
ps
ps
TXUSR
CLK
cycles
%
%
Module 3 of 4
18

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