XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 99

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 35: IOB Output Switching Characteristics Standard Adjustments (Continued)
Description
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI, 2.5V
LVDCI, 1.8V
LVDCI, 1.5V
LVDCI, 2.5V, Half-Impedance
LVDCI, 1.8V, Half-Impedance
LVDCI, 1.5V, Half-Impedance
HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
HSLVDCI, 1.8V
HSLVDCI, 2.5V
HSLVDCI, 3.3V
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
HSTL (High-Speed Transceiver Logic), Class I, with DCI
HSTL, Class II, with DCI
HSTL, Class III, with DCI
HSTL, Class IV, with DCI
HSTL, Class I, 1.8V, with DCI
HSTL, Class II, 1.8V, with DCI
HSTL, Class III, 1.8V, with DCI
HSTL, Class IV, 1.8V, with DCI
SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI
SSTL, Class II, 1.8V, with DCI
SSTL, Class I, 2.5V, with DCI
SSTL, Class II, 2.5V, with DCI
DS083 (v4.7) November 5, 2007
Product Specification
IOSTANDARD
Timing
Attribute
Parameter
HSTL_II
T
OHSTL_II
HSTL_III
T
OHSTL_IIII
HSTL_IV
T
OHSTL_IV
HSTL_I_18
T
OHSTL_I_18
HSTL_II_18
T
OHSTL_II_18
HSTL_III_18
T
OHSTL_IIII_18
HSTL_IV_18
T
OHSTL_IV_18
SSTL18_I
T
OSSTL18_I
SSTL18_II
T
OSSTL18_II
SSTL2_I
T
OSSTL2_I
SSTL2_II
T
OSSTL2_II
LVDCI_33
T
OLVDCI_33
LVDCI_25
T
OLVDCI_25
LVDCI_18
T
OLVDCI_18
LVDCI_15
T
OLVDCI_15
LVDCI_DV2_25
T
OLVDCI_DV2_25
LVDCI_DV2_18
T
OLVDCI_DV2_18
LVDCI_DV2_15
T
OLVDCI_DV2_15
HSLVDCI_15
T
OHSLVDCI_15
HSLVDCI_18
T
OHSLVDCI_18
HSLVDCI_25
T
OHSLVDCI_25
HSLVDCI_33
T
OHSLVDCI_33
GTL_DCI
T
OGTL_DCI
GTLP_DCI
T
OGTLP_DCI
HSTL_I_DCI
T
OHSTL_I_DCI
HSTL_II_DCI
T
OHSTL_II_DCI
HSTL_III_DCI
T
OHSTL_III_DCI
HSTL_IV_DCI
T
OHSTL_IV_DCI
HSTL_I_DCI_18
T
OHSTL_I_DCI_18
HSTL_II_DCI_18
T
OHSTL_II_DCI_18
HSTL_III_DCI_18
T
OHSTL_III_DCI_18
HSTL_IV_DCI_18
T
OHSTL_IV_DCI_18
SSTL18_I_DCI
T
OSSTL18_I_DCI
SSTL18_II_DCI
T
OSSTL18_II_DCI
SSTL2_I_DCI
T
OSSTL2_I_DCI
SSTL2_II_DCI
T
OSSTL2_II_DCI
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Speed Grade
-7
-6
-5
Units
0.30
0.35
0.38
ns
0.31
0.35
0.39
ns
0.15
0.17
0.19
ns
0.56
0.64
0.70
ns
0.30
0.35
0.38
ns
0.36
0.41
0.45
ns
0.19
0.22
0.24
ns
0.80
0.92
1.01
ns
0.45
0.51
0.56
ns
0.63
0.72
0.79
ns
0.22
0.25
0.27
ns
0.72
0.83
0.91
ns
0.56
0.64
0.71
ns
0.65
0.75
0.82
ns
1.00
1.15
1.26
ns
0.06
0.07
0.08
ns
0.30
0.34
0.38
ns
0.60
0.69
0.76
ns
1.00
1.15
1.26
ns
0.65
0.75
0.82
ns
0.56
0.64
0.71
ns
0.72
0.83
0.91
ns
1.21
1.39
1.53
ns
0.05
0.06
0.07
ns
0.55
0.63
0.69
ns
0.47
0.54
0.60
ns
0.31
0.36
0.40
ns
1.81
2.08
2.29
ns
0.55
0.63
0.70
ns
0.24
0.28
0.31
ns
0.35
0.40
0.44
ns
1.48
1.70
1.87
ns
0.54
0.62
0.68
ns
0.24
0.28
0.31
ns
0.48
0.56
0.61
ns
0.48
0.56
0.61
ns
Module 3 of 4
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