XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 123

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Block RAM Library Primitives
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Block RAM Error Correction Code
Table 4-4: Available Byte-wide Write Enables (Continued)
When the RAMB36 is configured for a 36-bit or 18-bit wide data path, any port can restrict
writing to specified byte locations within the data word. If configured in READ_FIRST
mode, the DO bus shows the previous content of the whole addressed word. In
WRITE_FIRST mode, DO shows a combination of the newly written enabled byte(s), and
the initial memory contents of the unwritten bytes.
X-Ref Target - Figure 4-8
Both block RAM and FIFO implementations of the 36 Kb block RAM support a 64-bit Error
Correction Code (ECC) implementation. The code is used to detect single and double-bit
errors in block RAM data read out. Single-bit errors are then corrected in the output data.
The Virtex-5 FPGA block RAM library primitives, RAMB18 and RAMB36, are the basic
building blocks for all block RAM configurations. Other block RAM primitives and macros
are based on these primitives. Some block RAM attributes can only be configured using
one of these primitives (e.g., pipeline register, cascade, etc.). See the
section.
The input and output data buses are represented by two buses for 9-bit width (8 + 1), 18-bit
width (16 + 2), and 36-bit width (32 + 4) configurations. The ninth bit associated with each
byte can store parity/error correction bits or serve as additional data bits. No specific
function is performed on the ninth bit. The separate bus for parity bits facilitates some
designs. However, other designs safely use a 9-bit, 18-bit, or 36-bit bus by merging the
regular data bus with the parity bus. Read/write and storage operations are identical for
all bits, including the parity bits.
RAMB18
RAMB18SDP
ADDR
Primitive
Figure 4-8: Byte-wide Write Operation Waveforms (x36 WRITE_FIRST)
CLK
WE
DO
EN
DI
Disabled
0000
Maximum Bit Width
XXXX
www.xilinx.com
aa
Read
18
36
MEM(aa)
bb
MEM(bb)=1111
1111
1111
Write
Number of Byte-wide Write Enables
1111
0011
2222
bb
MEM(bb)=1122
Byte Write
Block RAM Library Primitives
1122
2
4
Block RAM Attributes
cc
ug190_4_10_032106
XXXX
Read
MEM(cc)
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