XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 161

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Block RAM and FIFO ECC Primitive
Figure 4-29
FIFO36_72 ECC primitive. The FIFO36_72 only supports standard mode.
X-Ref Target - Figure 4-29
X-Ref Target - Figure 4-30
shows the block RAM (RAMB36SDP) ECC primitive.
Figure 4-29: RAMB36SDP: Block RAM ECC Primitive
Figure 4-30: FIFO36_72: FIFO ECC Primitive
www.xilinx.com
DI[63:0]
DIP[7:0]
(Decode Only)
WRADDR[8:0]
RDADDR[8:0]
WREN
RDEN
SSR
WRCLK
RDCLK
DI[63:0]
DIP[7:0]
WREN
RDEN
RST
WRCLK
RDCLK
RAMB36SDP
FIFO36_72
ECCPARITY[7:0]
ECCPARITY[7:0]
ALMOSTEMPTY
WRCOUNT[8:0]
RDCOUNT[8:0]
ALMOSTFULL
Encode Only)
(Standard or
DBITERR
SBITERR
SBITERR
DBITERR
DOP[7:0]
DO[63:0]
DOP[7:0]
DO[63:0]
WRERR
RDERR
EMPTY
FULL
ug190_4_26_022207
ug190_4_34_022207
Built-in Error Correction
Figure 4-30
shows the
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