XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 168

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 4: Block RAM
168
ECC Timing Characteristics
Standard ECC Write Timing
Standard ECC Read Timing
The various ECC timing parameters are also shown in
Since write clock and read clock are independent of each other, all write timing in
Figure 4-31
RDCLK.
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DO_REG = 0
DO_REG = 1
At time TRCCK_EN, before time T1W, write enable becomes valid at the WREN input
of the block RAM.
At time TRCCK_ADDR, before time T1W, write address a becomes valid at the
WRADDR[8:0] inputs of the block RAM. WRADDR input is not needed for FIFO.
At time TRDCK_DI_ECC (standard ECC), before time T1W, write data A (hex)
becomes valid at the DI[63:0] inputs of the block RAM.
At time TRCKO_ECC_PARITY (standard ECC), after time T1W, ECC parity data PA
(hex) becomes valid at the ECCPARITY[7:0] output pins of the block RAM.
At time TRCCK_EN, before time T1R, read enable becomes valid at the RDEN input
of the block RAM.
At time TRCCK_ADDR, before time T1R, write address a becomes valid at the
RDADDR[8:0] inputs of the block RAM. RDADDR input is not needed for FIFO.
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At time TRCKO_DO (latch mode), after time T1R, data A (hex) becomes valid at
the DO[63:0] output pins of the block RAM.
At time TRCKO_DOP (latch mode), after time T1R, data PA (hex) becomes valid
at the DOP[7:0] output pins of the block RAM.
At time TRCKO_ECC_SBITERR (latch mode), after time T1R, SBITERR is asserted
if single-bit error is detected and corrected on data set A.
At time TRCKO_ECC_DBITERR (latch mode), after time T2R, DBITERR is
asserted if double-bit error is detected on data set B.
At time TRCKO_DO (register mode), after time T2R, data A (hex) becomes valid
at the DO[63:0] output pins of the block RAM.
At time TRCKO_DOP (register mode), after time T2R, data PA (hex) becomes
valid at the DOP[7:0] output pins of the block RAM.
At time TRCKO_ECCR_SBITERR (register mode), after time T2R, SBITERR is
asserted if single-bit error is detected and corrected on data set A.
At time TRCKO_ECCR_DBITERR (register mode), after time T3R, DBITERR is
asserted if double-bit error is detected on data set B.
is referenced to WRCLK. All read timing in
www.xilinx.com
(Figure
(Figure
4-31)
4-32)
Figure 4-31
Figure 4-32
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
and
is referenced to
Figure
4-32.