XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 170

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 4: Block RAM
Table 4-25: Block RAM ECC Mode Timing Parameters (Continued)
170
Notes:
1. T
2. T
3. T
4. T
Clock to ECC Delays
T
T
(encode-only mode)
T
T
Data Sheet.
RCKO_ECCR_DBITERR
RCKO_ECCR_SBITERR
RCKO_ECC_DBITERR
RCKO_ECC_SBITERR
T
RDCK_DI_ECC
RCKO_DO
RCKO_ECC_PARITY
RCKO_ECC_SBITERR
RCKO_ECC_PARITY
Parameter
Creating a Deliberate Error in a 72-bit Word
Creating Eight Parity Bits for a 64-bit Word
Inserting a Single or Double Bit Error into a 72-bit Word
includes parity output (T
/T
RCKD_DI_ECC
, T
and T
RCKO_ECC_SBITERR
(3)
(3)
(3)
(4)
(4)
To deliberately create an error in a 72-bit word, configure the ECC decode-only mode and
create a 72-bit word with one or two bit errors. Write the word into the block RAM.
Reading the 72-bit word automatically corrects the single-bit error and asserts the
SBITERR error flag or it detects the double-bit error and asserts the DBITERR error flag.
Using logic external to the block RAM (a large number of XOR circuits), eight parity bits
can be created for a 64-bit word. However, using ECC encoder-only mode, the eight parity
bits can be automatically created without additional logic by writing any 64-bit word into
a separate block RAM. The encoded 8-bit ECC parity data is immediately available, or the
complete 72-bit word can be read out.
By reading a 72-bit word and selectively modifying one or two bits, then writing all 72 bits
into the block RAM under test in ECC decode-only mode, a single or double bit error can
be inserted.
RCKO_ECC_DBITERR
Double-Bit-Error
Double-Bit-Error
Single-Bit-Error
Single-Bit-Error
include the parity input T
Parity Output
Clock to ECC
Clock to ECC
Clock to ECC
Clock to ECC
Clock to ECC
Function
Output
Output
Output
Output
RCKO_DOP
, and T
are combined into the T
RCKO_ECC_DBITERR
).
ECCPARITY
DBITERR
DBITERR
SBITERR
SBITERR
Control
Signal
www.xilinx.com
RDCK_DIP_ECC
are combined into the T
RCKO_ECCR
stable at the ECCPARITY outputs of the block RAM (in
encode-only mode).
Time after RDCLK that the single-bit-error signal is
stable at the SBITERR output of the block RAM
(without output register).
Time after RDCLK that the single-bit-error signal is
stable at the SBITERR output of the block RAM (with
output register).
Time after RDCLK that the double-bit-error signal is
stable at the DBITERR output of the block RAM
(without output register).
Time after RDCLK that the double-bit-error signal is
stable at the DBITERR output of the block RAM (with
output register).
Time after WRCLK that the ECC parity signals are
/T
RCKD_DIP_ECC
parameter in the Virtex-5 FPGA Data Sheet.
.
RCKO_ECC
Description
parameter in the Virtex-5 FPGA
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010