XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 200

• Manufacturer Part Number: XC5VLX50T-1FFG1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

• Total Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 7200
• No. Of Gates: 50000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 480
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1564

Chapter 5: Configurable Logic Blocks (CLBs)
CLB / Slice Timing Models
200
to create an adder/accumulator. CYINIT is the CIN of the first bit in a carry chain. The
CYINIT value can be 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry
bit). The CIN input is used to cascade slices to form a longer carry chain. The O outputs
contain the sum of the addition/subtraction. The CO outputs compute the carry out for
each bit. CO3 is connected to COUT output of a slice to form a longer carry chain by
cascading multiple slices. The propagation delay for an adder increases linearly with the
number of bits in the operand, as more carry chains are cascaded. The carry chain can be
implemented with a storage element or a flip-flop in the same slice.
Due to the large size and complexity of Virtex-5 FPGAs, understanding the timing
associated with the various paths and functional elements is a difficult and important task.
Although it is not necessary to understand the various timing parameters to implement
most designs using Xilinx software, a thorough timing model can assist advanced users in
analyzing critical paths or planning speed-sensitive designs.
Three timing model sections are described:
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•
•
Use the models in this chapter in conjunction with both the Xilinx Timing Analyzer
software (TRCE) and the section on switching characteristics in the Virtex-5 FPGA Data
Sheet. All pin names, parameter names, and paths are consistent with the post-route timing
and pre-route static timing reports. Most of the timing parameters found in the section on
switching characteristics are described in this chapter.
All timing parameters reported in the Virtex-5 FPGA Data Sheet are associated with slices
and CLBs. The following sections correspond to specific switching characteristics sections
in the Virtex-5 FPGA Data Sheet:
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•
•
•
Functional element diagram – basic architectural schematic illustrating pins and
connections
Timing parameters – definitions of Virtex-5 FPGA Data Sheet timing parameters
Timing Diagram - illustrates functional element timing parameters relative to each
other
General Slice Timing Model and Parameters
Slice Distributed RAM Timing Model and Parameters (Available in SLICEM only)
(CLB Distributed RAM Switching Characteristics)
Slice SRL Timing Model and Parameters (Available in SLICEM only)
Switching Characteristics)
Slice Carry-Chain Timing Model and Parameters
Characteristics)
www.xilinx.com
(CLB Switching Characteristics)
(CLB Application Switching
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
(CLB SRL